From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Subject: Re: [regression] nct6775 does not load in 5.4 and 5.5, bisected to b84398d6d7f90080 Date: Mon, 24 Feb 2020 12:37:31 +0200 Message-ID: <20200224103731.GA10400@smile.fi.intel.com> References: <1bdbac08-86f8-2a57-2b0d-8cd2beb2a1c0@roeck-us.net> <85356d1a-f90d-e94d-16eb-1071d4e94753@roeck-us.net> <20200224101800.GJ2667@lahna.fi.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20200224101800.GJ2667@lahna.fi.intel.com> Sender: linux-hwmon-owner@vger.kernel.org To: Mika Westerberg Cc: Guenter Roeck , Martin Volf , Jean Delvare , Wolfram Sang , linux-i2c@vger.kernel.org, linux-hwmon@vger.kernel.org, Linux Kernel Mailing List , Jarkko Nikula List-Id: linux-i2c@vger.kernel.org On Mon, Feb 24, 2020 at 12:18:00PM +0200, Mika Westerberg wrote: > On Sat, Feb 22, 2020 at 01:26:48PM -0800, Guenter Roeck wrote: > > On 2/22/20 12:49 PM, Martin Volf wrote: > > > On Sat, Feb 22, 2020 at 8:05 PM Guenter Roeck wrote: ... > > > devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2); I'm wondering if pci_dev_is_present(...); returns false here. > > > pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr); > > > > > > res = &tco_res[ICH_RES_IO_SMI]; > > > res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF; > > > res->end = res->start + 3; > > > res->flags = IORESOURCE_IO; > > > > > > base_addr is 0xffffffff after pci_bus_read_config_dword() call. > > > ACPIBASE_SMI_OFF is 0x030, therefore res->start is 0x2e. > > > Not that I understand even a bit of this... > > > > > > > Outch. This means that the code is broken. ACPIBASE is not configured, > > or disabled, or the code reads from the wrong PCI configuration register. > > What I don't understand is why this works with v5.3 kernels; the code > > looks just as bad there for me. I must be missing something. Either case, > > the only thing you can really do at this point is to blacklist the > > iTCO_wdt driver. > > Indeed it looks like the code reads from a register that is not there > anymore in this generation hardware, or something like that. It tries to > read the PMC (1f.2) register add address 0x40 which is supposed to be > base of ACPI PM registers but that does not seem to exist any more in > newer chipset. > > We'll look into this more and return back. -- With Best Regards, Andy Shevchenko