From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH 17/28] dt-bindings: mmc: Fix up clk-phase-sd-hs in an example Date: Fri, 27 Mar 2020 13:08:07 -0600 Message-ID: <20200327190807.GA1996@bogus> References: <20200317093922.20785-1-lkundrak@v3.sk> <20200317093922.20785-18-lkundrak@v3.sk> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20200317093922.20785-18-lkundrak-NGH9Lh4a5iE@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Lubomir Rintel Cc: Linus Walleij , Bartosz Golaszewski , Thomas Gleixner , Jason Cooper , Marc Zyngier , Mauro Carvalho Chehab , Ulf Hansson , Kishon Vijay Abraham I , Alessandro Zummo , Alexandre Belloni , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Andrew Lunn , Gregory Clement , Daniel Mack , Haojian Zhuang , Robert Jarzmik , devicetree-u79uwXL29TZNg+MwTxZMZA@public.gmane.org List-Id: linux-i2c@vger.kernel.org On Tue, Mar 17, 2020 at 10:39:11AM +0100, Lubomir Rintel wrote: > This way the validator can know that the two cells constitute a singlej > pair of clock phase degrees value, not separate items Otherwise it is > unhappy: > > mmc-controller.example.dt.yaml: mmc@ab000000: clk-phase-sd-hs:0: > [63] is too short > mmc-controller.example.dt.yaml: mmc@ab000000: clk-phase-sd-hs:1: > [72] is too short I'm going to fix this in the tools to allow either form. > > Signed-off-by: Lubomir Rintel > --- > Documentation/devicetree/bindings/mmc/mmc-controller.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml > index 8fded83c519ad..c9384ed685b8f 100644 > --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml > +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml > @@ -363,7 +363,7 @@ examples: > keep-power-in-suspend; > wakeup-source; > mmc-pwrseq = <&sdhci0_pwrseq>; > - clk-phase-sd-hs = <63>, <72>; > + clk-phase-sd-hs = <63 72>; > }; > > - | > -- > 2.25.1 >