From: Jean Delvare <jdelvare@suse.de>
To: Adam Honse <calcprogrammer1@gmail.com>
Cc: linux-i2c@vger.kernel.org
Subject: Re: [PATCH] i2c: Detect secondary SMBus controller on AMD AM4 chipsets
Date: Fri, 10 Apr 2020 09:55:28 +0200 [thread overview]
Message-ID: <20200410095528.1a6d3d99@endymion> (raw)
In-Reply-To: <CAD_xsFPMx5zPuqEcaCq3urdFzrpvrY1NuoH-WqTWvNPNXn+sVA@mail.gmail.com>
Hi Adam,
On Sat, 4 Apr 2020 13:20:58 -0500, Adam Honse wrote:
> I'm not sure what all chipsets are covered by the KERNCZ ID. We have found
> that the secondary bus exists on all AM4 chipsets and on X399 as well.
> Considering the older Hudson 2 has the same secondary bus (which is
> correctly detected without a patch on my old FM1 home server, also at
> 0x0B20) I would believe the secondary bus exists on all chipsets. I could
> add a revision check though. My X370 reports (rev 59) in lspci.
Fair enough, let's assume it's present on all chipsets and we can
refine later if needed.
If so, can you please merge the kerncz check with the hudson2 check
right before as we do the same for both?
Then please submit with your Signed-off-by statement and I'll review
and ack the patch for Wolfram to commit.
Thanks,
--
Jean Delvare
SUSE L3 Support
next prev parent reply other threads:[~2020-04-10 7:55 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-29 17:44 [PATCH] i2c: Detect secondary SMBus controller on AMD AM4 chipsets Adam Honse
2020-03-30 16:31 ` Jean Delvare
[not found] ` <CAD_xsFPMx5zPuqEcaCq3urdFzrpvrY1NuoH-WqTWvNPNXn+sVA@mail.gmail.com>
2020-04-10 7:55 ` Jean Delvare [this message]
-- strict thread matches above, loose matches on Subject: below --
2020-04-10 20:48 Adam Honse
2020-04-14 7:34 ` Jean Delvare
2020-04-14 7:35 ` Jean Delvare
2020-04-15 10:28 ` Wolfram Sang
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