* [PATCH V8 1/8] soc: qcom: geni: Support for ICC voting
2020-06-23 10:38 [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana
@ 2020-06-23 10:38 ` Akash Asthana
2020-06-23 10:38 ` [PATCH V8 2/8] soc: qcom-geni-se: Add interconnect support to fix earlycon crash Akash Asthana
` (7 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Akash Asthana @ 2020-06-23 10:38 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, evgreen, linux-kernel, Akash Asthana
Add necessary macros and structure variables to support ICC BW
voting from individual SE drivers.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
Changes in V2:
- As per Bjorn's comment dropped enums for ICC paths, given the three
paths individual members
Changes in V3:
- Add geni_icc_get, geni_icc_vote_on and geni_icc_vote_off as helper API.
- Add geni_icc_path structure in common header
Changes in V4:
- As per Bjorn's comment print error message in geni_icc_get if return
value is not -EPROBE_DEFER.
- As per Bjorn's comment remove NULL on path before calling icc_set_bw
API.
- As per Bjorn's comment drop __func__ print.
- As per Matthias's comment, make ICC path a array instead of individual
member entry in geni_se struct.
Changes in V5:
- As per Matthias's comment defined enums for ICC paths.
- Integrate icc_enable/disable with power on/off call for driver.
- As per Matthias's comment added icc_path_names array to print icc path name
in failure case.
- As per Georgi's suggestion assume peak_bw = avg_bw if not mentioned.
Changes in V6:
- Addressed nitpicks from Matthias.
Changes in V7:
- As per Matthias's comment removed usage of peak_bw variable because we don't
have explicit peak requirement, we were voting peak = avg and this can be
tracked using single variable for avg bw.
- As per Matthias's comment improved print log.
Changes in V8:
- No change.
Note: I have ignored below check patch suggestion because it was throwing
compilation error as 'icc_ddr' is not compile time comstant.
WARNING: char * array declaration might be better as static const
- FILE: drivers/soc/qcom/qcom-geni-se.c:726:
- const char *icc_names[] = {"qup-core", "qup-config", icc_ddr};
drivers/soc/qcom/qcom-geni-se.c | 82 +++++++++++++++++++++++++++++++++++++++++
include/linux/qcom-geni-se.h | 38 +++++++++++++++++++
2 files changed, 120 insertions(+)
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index 7d622ea..950e347 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -92,6 +92,9 @@ struct geni_wrapper {
struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
};
+static const char * const icc_path_names[] = {"qup-core", "qup-config",
+ "qup-memory"};
+
#define QUP_HW_VER_REG 0x4
/* Common SE registers */
@@ -720,6 +723,85 @@ void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
}
EXPORT_SYMBOL(geni_se_rx_dma_unprep);
+int geni_icc_get(struct geni_se *se, const char *icc_ddr)
+{
+ int i, err;
+ const char *icc_names[] = {"qup-core", "qup-config", icc_ddr};
+
+ for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
+ if (!icc_names[i])
+ continue;
+
+ se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]);
+ if (IS_ERR(se->icc_paths[i].path))
+ goto err;
+ }
+
+ return 0;
+
+err:
+ err = PTR_ERR(se->icc_paths[i].path);
+ if (err != -EPROBE_DEFER)
+ dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n",
+ icc_names[i], err);
+ return err;
+
+}
+EXPORT_SYMBOL(geni_icc_get);
+
+int geni_icc_set_bw(struct geni_se *se)
+{
+ int i, ret;
+
+ for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
+ ret = icc_set_bw(se->icc_paths[i].path,
+ se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw);
+ if (ret) {
+ dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n",
+ icc_path_names[i], ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(geni_icc_set_bw);
+
+/* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */
+int geni_icc_enable(struct geni_se *se)
+{
+ int i, ret;
+
+ for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
+ ret = icc_enable(se->icc_paths[i].path);
+ if (ret) {
+ dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n",
+ icc_path_names[i], ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(geni_icc_enable);
+
+int geni_icc_disable(struct geni_se *se)
+{
+ int i, ret;
+
+ for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
+ ret = icc_disable(se->icc_paths[i].path);
+ if (ret) {
+ dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n",
+ icc_path_names[i], ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(geni_icc_disable);
+
static int geni_se_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
index dd46494..80dbc01 100644
--- a/include/linux/qcom-geni-se.h
+++ b/include/linux/qcom-geni-se.h
@@ -6,6 +6,8 @@
#ifndef _LINUX_QCOM_GENI_SE
#define _LINUX_QCOM_GENI_SE
+#include <linux/interconnect.h>
+
/* Transfer mode supported by GENI Serial Engines */
enum geni_se_xfer_mode {
GENI_SE_INVALID,
@@ -25,6 +27,17 @@ enum geni_se_protocol_type {
struct geni_wrapper;
struct clk;
+enum geni_icc_path_index {
+ GENI_TO_CORE,
+ CPU_TO_GENI,
+ GENI_TO_DDR
+};
+
+struct geni_icc_path {
+ struct icc_path *path;
+ unsigned int avg_bw;
+};
+
/**
* struct geni_se - GENI Serial Engine
* @base: Base Address of the Serial Engine's register block
@@ -33,6 +46,7 @@ struct clk;
* @clk: Handle to the core serial engine clock
* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
* @clk_perf_tbl: Table of clock frequency input to serial engine clock
+ * @icc_paths: Array of ICC paths for SE
*/
struct geni_se {
void __iomem *base;
@@ -41,6 +55,7 @@ struct geni_se {
struct clk *clk;
unsigned int num_clk_levels;
unsigned long *clk_perf_tbl;
+ struct geni_icc_path icc_paths[3];
};
/* Common SE registers */
@@ -229,6 +244,21 @@ struct geni_se {
#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
+/*
+ * Define bandwidth thresholds that cause the underlying Core 2X interconnect
+ * clock to run at the named frequency. These baseline values are recommended
+ * by the hardware team, and are not dynamically scaled with GENI bandwidth
+ * beyond basic on/off.
+ */
+#define CORE_2X_19_2_MHZ 960
+#define CORE_2X_50_MHZ 2500
+#define CORE_2X_100_MHZ 5000
+#define CORE_2X_150_MHZ 7500
+#define CORE_2X_200_MHZ 10000
+#define CORE_2X_236_MHZ 16383
+
+#define GENI_DEFAULT_BW Bps_to_icc(1000)
+
#if IS_ENABLED(CONFIG_QCOM_GENI_SE)
u32 geni_se_get_qup_hw_version(struct geni_se *se);
@@ -416,5 +446,13 @@ int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
+
+int geni_icc_get(struct geni_se *se, const char *icc_ddr);
+
+int geni_icc_set_bw(struct geni_se *se);
+
+int geni_icc_enable(struct geni_se *se);
+
+int geni_icc_disable(struct geni_se *se);
#endif
#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V8 2/8] soc: qcom-geni-se: Add interconnect support to fix earlycon crash
2020-06-23 10:38 [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana
2020-06-23 10:38 ` [PATCH V8 1/8] soc: qcom: geni: Support for ICC voting Akash Asthana
@ 2020-06-23 10:38 ` Akash Asthana
2020-06-23 10:38 ` [PATCH V8 3/8] i2c: i2c-qcom-geni: Add interconnect support Akash Asthana
` (6 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Akash Asthana @ 2020-06-23 10:38 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, evgreen, linux-kernel, Akash Asthana
QUP core clock is shared among all the SE drivers present on particular
QUP wrapper, the system will reset(unclocked access) if earlycon used after
QUP core clock is put to 0 from other SE drivers before real console comes
up.
As earlycon can't vote for it's QUP core need, to fix this add ICC
support to common/QUP wrapper driver and put vote for QUP core from
probe on behalf of earlycon and remove vote during earlycon exit call.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reported-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
Change in V3:
- Add geni_remove_earlycon_icc_vote API that will be used by earlycon
exit function to remove ICC vote for earlyconsole.
- Remove suspend/resume hook for geni-se driver as we are no longer
removing earlyconsole ICC vote from system suspend, we are removing
from earlycon exit.
Change in V4:
- As per Matthias comment make 'earlycon_wrapper' as static structure.
Changes in V5:
- Vote for core path only after checking whether "qcom_geni" earlycon is
actually present or not by traversing over structure "console_drivers".
Changes in V6:
- As per Matthias's comment removed NULL check for console_drivers global
struct, added NULL check for earlycon_wrapper in _remove_earlycon_icc_vote
API
- Addressed nitpicks from Andy.
Changes in V7:
- As per Matthias's comment removed usage of peak_bw variable because we don't
have explicit peak requirement, we were voting peak = avg and this can be
tracked using single variable for avg bw.
- As per Matthias's comment improved print log.
Changes in V8:
- No change.
drivers/soc/qcom/qcom-geni-se.c | 68 +++++++++++++++++++++++++++++++++++
drivers/tty/serial/qcom_geni_serial.c | 7 ++++
include/linux/qcom-geni-se.h | 2 ++
3 files changed, 77 insertions(+)
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index 950e347..e2a0ba2 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -3,6 +3,7 @@
#include <linux/acpi.h>
#include <linux/clk.h>
+#include <linux/console.h>
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
@@ -90,11 +91,14 @@ struct geni_wrapper {
struct device *dev;
void __iomem *base;
struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
+ struct geni_icc_path to_core;
};
static const char * const icc_path_names[] = {"qup-core", "qup-config",
"qup-memory"};
+static struct geni_wrapper *earlycon_wrapper;
+
#define QUP_HW_VER_REG 0x4
/* Common SE registers */
@@ -802,11 +806,38 @@ int geni_icc_disable(struct geni_se *se)
}
EXPORT_SYMBOL(geni_icc_disable);
+void geni_remove_earlycon_icc_vote(void)
+{
+ struct geni_wrapper *wrapper;
+ struct device_node *parent;
+ struct device_node *child;
+
+ if (!earlycon_wrapper)
+ return;
+
+ wrapper = earlycon_wrapper;
+ parent = of_get_next_parent(wrapper->dev->of_node);
+ for_each_child_of_node(parent, child) {
+ if (!of_device_is_compatible(child, "qcom,geni-se-qup"))
+ continue;
+ wrapper = platform_get_drvdata(of_find_device_by_node(child));
+ icc_put(wrapper->to_core.path);
+ wrapper->to_core.path = NULL;
+
+ }
+ of_node_put(parent);
+
+ earlycon_wrapper = NULL;
+}
+EXPORT_SYMBOL(geni_remove_earlycon_icc_vote);
+
static int geni_se_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct resource *res;
struct geni_wrapper *wrapper;
+ struct console __maybe_unused *bcon;
+ bool __maybe_unused has_earlycon = false;
int ret;
wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);
@@ -829,6 +860,43 @@ static int geni_se_probe(struct platform_device *pdev)
}
}
+#ifdef CONFIG_SERIAL_EARLYCON
+ for_each_console(bcon) {
+ if (!strcmp(bcon->name, "qcom_geni")) {
+ has_earlycon = true;
+ break;
+ }
+ }
+ if (!has_earlycon)
+ goto exit;
+
+ wrapper->to_core.path = devm_of_icc_get(dev, "qup-core");
+ if (IS_ERR(wrapper->to_core.path))
+ return PTR_ERR(wrapper->to_core.path);
+ /*
+ * Put minmal BW request on core clocks on behalf of early console.
+ * The vote will be removed earlycon exit function.
+ *
+ * Note: We are putting vote on each QUP wrapper instead only to which
+ * earlycon is connected because QUP core clock of different wrapper
+ * share same voltage domain. If core1 is put to 0, then core2 will
+ * also run at 0, if not voted. Default ICC vote will be removed ASA
+ * we touch any of the core clock.
+ * core1 = core2 = max(core1, core2)
+ */
+ ret = icc_set_bw(wrapper->to_core.path, GENI_DEFAULT_BW,
+ GENI_DEFAULT_BW);
+ if (ret) {
+ dev_err(&pdev->dev, "%s: ICC BW voting failed for core: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ if (of_get_compatible_child(pdev->dev.of_node, "qcom,geni-debug-uart"))
+ earlycon_wrapper = wrapper;
+ of_node_put(pdev->dev.of_node);
+#endif
+exit:
dev_set_drvdata(dev, wrapper);
dev_dbg(dev, "GENI SE Driver probed\n");
return devm_of_platform_populate(dev);
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index 457c0bf..a4468db 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -1121,6 +1121,12 @@ static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
struct console *con) { }
#endif
+static int qcom_geni_serial_earlycon_exit(struct console *con)
+{
+ geni_remove_earlycon_icc_vote();
+ return 0;
+}
+
static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
const char *opt)
{
@@ -1166,6 +1172,7 @@ static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
dev->con->write = qcom_geni_serial_earlycon_write;
+ dev->con->exit = qcom_geni_serial_earlycon_exit;
dev->con->setup = NULL;
qcom_geni_serial_enable_early_read(&se, dev->con);
diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
index 80dbc01..743dd97 100644
--- a/include/linux/qcom-geni-se.h
+++ b/include/linux/qcom-geni-se.h
@@ -454,5 +454,7 @@ int geni_icc_set_bw(struct geni_se *se);
int geni_icc_enable(struct geni_se *se);
int geni_icc_disable(struct geni_se *se);
+
+void geni_remove_earlycon_icc_vote(void);
#endif
#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V8 3/8] i2c: i2c-qcom-geni: Add interconnect support
2020-06-23 10:38 [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana
2020-06-23 10:38 ` [PATCH V8 1/8] soc: qcom: geni: Support for ICC voting Akash Asthana
2020-06-23 10:38 ` [PATCH V8 2/8] soc: qcom-geni-se: Add interconnect support to fix earlycon crash Akash Asthana
@ 2020-06-23 10:38 ` Akash Asthana
2020-06-23 10:38 ` [PATCH V8 4/8] tty: serial: qcom_geni_serial: " Akash Asthana
` (5 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Akash Asthana @ 2020-06-23 10:38 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, evgreen, linux-kernel, Akash Asthana
Get the interconnect paths for I2C based Serial Engine device
and vote according to the bus speed of the driver.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Wolfram Sang <wsa@kernel.org>
---
Changes in V2:
- As per Bjorn's comment, removed se == NULL check from geni_i2c_icc_get
- As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure
- As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
path handle
- As per Matthias comment, added error handling for icc_set_bw call
Changes in V3:
- As per Matthias comment, use common library APIs defined in geni-se
driver for ICC functionality.
Changes in V4:
- Move peak_bw guess as twice of avg_bw if nothing mentioned explicitly
to ICC core.
Changes in V5:
- Use icc_enable/disable in power on/off call.
Changes in V6:
- No changes
Changes in V7:
- As per Matthias's comment removed usage of peak_bw variable because we don't
have explicit peak requirement, we were voting peak = avg and this can be
tracked using single variable for avg bw.
Changes in V8:
- No change.
drivers/i2c/busses/i2c-qcom-geni.c | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 18d1e4f..32b2a99 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -557,6 +557,22 @@ static int geni_i2c_probe(struct platform_device *pdev)
gi2c->adap.dev.of_node = dev->of_node;
strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
+ ret = geni_icc_get(&gi2c->se, "qup-memory");
+ if (ret)
+ return ret;
+ /*
+ * Set the bus quota for core and cpu to a reasonable value for
+ * register access.
+ * Set quota for DDR based on bus speed.
+ */
+ gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
+ gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
+ gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out);
+
+ ret = geni_icc_set_bw(&gi2c->se);
+ if (ret)
+ return ret;
+
ret = geni_se_resources_on(&gi2c->se);
if (ret) {
dev_err(dev, "Error turning on resources %d\n", ret);
@@ -579,6 +595,10 @@ static int geni_i2c_probe(struct platform_device *pdev)
return ret;
}
+ ret = geni_icc_disable(&gi2c->se);
+ if (ret)
+ return ret;
+
dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
gi2c->suspended = 1;
@@ -623,7 +643,7 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
gi2c->suspended = 1;
}
- return 0;
+ return geni_icc_disable(&gi2c->se);
}
static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
@@ -631,6 +651,10 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
int ret;
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
+ ret = geni_icc_enable(&gi2c->se);
+ if (ret)
+ return ret;
+
ret = geni_se_resources_on(&gi2c->se);
if (ret)
return ret;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V8 4/8] tty: serial: qcom_geni_serial: Add interconnect support
2020-06-23 10:38 [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana
` (2 preceding siblings ...)
2020-06-23 10:38 ` [PATCH V8 3/8] i2c: i2c-qcom-geni: Add interconnect support Akash Asthana
@ 2020-06-23 10:38 ` Akash Asthana
2020-06-23 10:38 ` [PATCH V8 5/8] spi: spi-geni-qcom: Combine the clock setting code Akash Asthana
` (4 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Akash Asthana @ 2020-06-23 10:38 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, evgreen, linux-kernel, Akash Asthana
Get the interconnect paths for Uart based Serial Engine device
and vote according to the baud rate requirement of the driver.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
Changes in V2:
- As per Bjorn's comment, removed se == NULL check from geni_serial_icc_get
- As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure
- As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
path handle
- As per Matthias comment, added error handling for icc_set_bw call
Changes in V3:
- As per Matthias comment, use common library APIs defined in geni-se
driver for ICC functionality.
Changes in V4:
- As per Mark's comment move peak_bw guess as twice of avg_bw if
nothing mentioned explicitly to ICC core.
- As per Matthias's comment select core clock BW based on baud rate.
If it's less than 115200 go for GENI_DEFAULT_BW else CORE_2X_50_MHZ
Changes in V5:
- Add icc_enable/disable to power on/off call.
- Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw
from probe so that when resume/icc_enable is called NOC are running at
some non-zero value. No need to call icc_disable after BW vote because
console devices are expected to be in active state from the probe itself
and qcom_geni_serial_pm(STATE_OFF) will be called for non-console ones.
Changes in V6:
- No change
Changes in V7:
- As per Matthias's comment removed usage of peak_bw variable because we don't
have explicit peak requirement, we were voting peak = avg and this can be
tracked using single variable for avg bw.
Changes in V8:
- No change.
drivers/tty/serial/qcom_geni_serial.c | 31 ++++++++++++++++++++++++++++---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index a4468db..f701c7e 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -945,6 +945,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
unsigned long clk_rate;
u32 ver, sampling_rate;
+ unsigned int avg_bw_core;
qcom_geni_serial_stop_rx(uport);
/* baud rate */
@@ -966,6 +967,16 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
ser_clk_cfg = SER_CLK_EN;
ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
+ /*
+ * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
+ * only.
+ */
+ avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
+ : GENI_DEFAULT_BW;
+ port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
+ port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
+ geni_icc_set_bw(&port->se);
+
/* parity */
tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
@@ -1235,11 +1246,14 @@ static void qcom_geni_serial_pm(struct uart_port *uport,
if (old_state == UART_PM_STATE_UNDEFINED)
old_state = UART_PM_STATE_OFF;
- if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
+ if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
+ geni_icc_enable(&port->se);
geni_se_resources_on(&port->se);
- else if (new_state == UART_PM_STATE_OFF &&
- old_state == UART_PM_STATE_ON)
+ } else if (new_state == UART_PM_STATE_OFF &&
+ old_state == UART_PM_STATE_ON) {
geni_se_resources_off(&port->se);
+ geni_icc_disable(&port->se);
+ }
}
static const struct uart_ops qcom_geni_console_pops = {
@@ -1337,6 +1351,17 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ ret = geni_icc_get(&port->se, NULL);
+ if (ret)
+ return ret;
+ port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
+ port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
+
+ /* Set BW for register access */
+ ret = geni_icc_set_bw(&port->se);
+ if (ret)
+ return ret;
+
port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
"qcom_geni_serial_%s%d",
uart_console(uport) ? "console" : "uart", uport->line);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V8 5/8] spi: spi-geni-qcom: Combine the clock setting code
2020-06-23 10:38 [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana
` (3 preceding siblings ...)
2020-06-23 10:38 ` [PATCH V8 4/8] tty: serial: qcom_geni_serial: " Akash Asthana
@ 2020-06-23 10:38 ` Akash Asthana
2020-06-23 10:56 ` Mark Brown
2020-06-23 10:38 ` [PATCH V8 6/8] spi: spi-geni-qcom: Add interconnect support Akash Asthana
` (3 subsequent siblings)
8 siblings, 1 reply; 13+ messages in thread
From: Akash Asthana @ 2020-06-23 10:38 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, evgreen, linux-kernel, Akash Asthana
From: Douglas Anderson <dianders@chromium.org>
There is code for adjusting the clock both in setup_fifo_params()
(called from prepare_message()) and in setup_fifo_xfer() (called from
transfer_one()). The code is the same. Abstract it out to a shared
function.
This is a no-op cleanup patch. The only change is to the error string
if we fail to set the clock. Since the two paths has marginally
different error messages I picked the clean one.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
---
This patch is introduced in V8 of the series.
drivers/spi/spi-geni-qcom.c | 70 ++++++++++++++++++++++-----------------------
1 file changed, 35 insertions(+), 35 deletions(-)
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index 0c534d1..f186906 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -192,14 +192,42 @@ static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
writel(word_len, se->base + SE_SPI_WORD_LEN);
}
+static int geni_spi_set_clock(struct spi_geni_master *mas, unsigned long clk_hz)
+{
+ u32 clk_sel, m_clk_cfg, idx, div;
+ struct geni_se *se = &mas->se;
+ int ret;
+
+ ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
+ if (ret) {
+ dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
+ return ret;
+ }
+
+ /*
+ * SPI core clock gets configured with the requested frequency
+ * or the frequency closer to the requested frequency.
+ * For that reason requested frequency is stored in the
+ * cur_speed_hz and referred in the consecutive transfer instead
+ * of calling clk_get_rate() API.
+ */
+ mas->cur_speed_hz = clk_hz;
+
+ clk_sel = idx & CLK_SEL_MSK;
+ m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
+ writel(clk_sel, se->base + SE_GENI_CLK_SEL);
+ writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
+
+ return 0;
+}
+
static int setup_fifo_params(struct spi_device *spi_slv,
struct spi_master *spi)
{
struct spi_geni_master *mas = spi_master_get_devdata(spi);
struct geni_se *se = &mas->se;
u32 loopback_cfg, cpol, cpha, demux_output_inv;
- u32 demux_sel, clk_sel, m_clk_cfg, idx, div;
- int ret;
+ u32 demux_sel;
loopback_cfg = readl(se->base + SE_SPI_LOOPBACK);
cpol = readl(se->base + SE_SPI_CPOL);
@@ -222,27 +250,16 @@ static int setup_fifo_params(struct spi_device *spi_slv,
demux_output_inv = BIT(spi_slv->chip_select);
demux_sel = spi_slv->chip_select;
- mas->cur_speed_hz = spi_slv->max_speed_hz;
mas->cur_bits_per_word = spi_slv->bits_per_word;
- ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, &idx, &div);
- if (ret) {
- dev_err(mas->dev, "Err setting clks ret(%d) for %ld\n",
- ret, mas->cur_speed_hz);
- return ret;
- }
-
- clk_sel = idx & CLK_SEL_MSK;
- m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
writel(cpha, se->base + SE_SPI_CPHA);
writel(cpol, se->base + SE_SPI_CPOL);
writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
- writel(clk_sel, se->base + SE_GENI_CLK_SEL);
- writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
- return 0;
+
+ return geni_spi_set_clock(mas, spi_slv->max_speed_hz);
}
static int spi_geni_prepare_message(struct spi_master *spi,
@@ -304,6 +321,7 @@ static void setup_fifo_xfer(struct spi_transfer *xfer,
u32 m_cmd = 0;
u32 spi_tx_cfg, len;
struct geni_se *se = &mas->se;
+ int ret;
/*
* Ensure that our interrupt handler isn't still running from some
@@ -328,27 +346,9 @@ static void setup_fifo_xfer(struct spi_transfer *xfer,
/* Speed and bits per word can be overridden per transfer */
if (xfer->speed_hz != mas->cur_speed_hz) {
- int ret;
- u32 clk_sel, m_clk_cfg;
- unsigned int idx, div;
-
- ret = get_spi_clk_cfg(xfer->speed_hz, mas, &idx, &div);
- if (ret) {
- dev_err(mas->dev, "Err setting clks:%d\n", ret);
+ ret = geni_spi_set_clock(mas, xfer->speed_hz);
+ if (ret)
return;
- }
- /*
- * SPI core clock gets configured with the requested frequency
- * or the frequency closer to the requested frequency.
- * For that reason requested frequency is stored in the
- * cur_speed_hz and referred in the consecutive transfer instead
- * of calling clk_get_rate() API.
- */
- mas->cur_speed_hz = xfer->speed_hz;
- clk_sel = idx & CLK_SEL_MSK;
- m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
- writel(clk_sel, se->base + SE_GENI_CLK_SEL);
- writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
}
mas->tx_rem_bytes = 0;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH V8 5/8] spi: spi-geni-qcom: Combine the clock setting code
2020-06-23 10:38 ` [PATCH V8 5/8] spi: spi-geni-qcom: Combine the clock setting code Akash Asthana
@ 2020-06-23 10:56 ` Mark Brown
0 siblings, 0 replies; 13+ messages in thread
From: Mark Brown @ 2020-06-23 10:56 UTC (permalink / raw)
To: Akash Asthana
Cc: gregkh, agross, bjorn.andersson, wsa, linux-i2c, linux-spi,
devicetree, swboyd, mgautam, linux-arm-msm, linux-serial, mka,
dianders, evgreen, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 390 bytes --]
On Tue, Jun 23, 2020 at 04:08:54PM +0530, Akash Asthana wrote:
> From: Douglas Anderson <dianders@chromium.org>
>
> There is code for adjusting the clock both in setup_fifo_params()
> (called from prepare_message()) and in setup_fifo_xfer() (called from
> transfer_one()). The code is the same. Abstract it out to a shared
> function.
Acked-by: Mark Brown <broonie@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V8 6/8] spi: spi-geni-qcom: Add interconnect support
2020-06-23 10:38 [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana
` (4 preceding siblings ...)
2020-06-23 10:38 ` [PATCH V8 5/8] spi: spi-geni-qcom: Combine the clock setting code Akash Asthana
@ 2020-06-23 10:38 ` Akash Asthana
2020-06-23 10:57 ` Mark Brown
2020-06-23 10:38 ` [PATCH V8 7/8] spi: spi-qcom-qspi: " Akash Asthana
` (2 subsequent siblings)
8 siblings, 1 reply; 13+ messages in thread
From: Akash Asthana @ 2020-06-23 10:38 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, evgreen, linux-kernel, Akash Asthana
Get the interconnect paths for SPI based Serial Engine device
and vote according to the current bus speed of the driver.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
---
Changes in V2:
- As per Bjorn's comment, removed se == NULL check from geni_spi_icc_get
- As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure
- As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
path handle
- As per Matthias comment, added error handling for icc_set_bw call
Changes in V3:
- As per Matthias's comment, use helper ICC function from geni-se driver.
Changes in V4:
- Move peak_bw guess as twice of avg_bw if nothing mentioned explicitly
to ICC core.
Changes in V5:
- Use icc_enable/disable in power on/off call.
- Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw
from probe so that when resume/icc_enable is called NOC are running at
some non-zero value. No need to call icc_disable after BW vote because
device will resume and suspend before probe return and will leave ICC in
disabled state.
Changes in V6:
- No change
Changes in V7:
- As per Matthias's comment removed usage of peak_bw variable because we don't
have explicit peak requirement, we were voting peak = avg and this can be
tracked using single variable for avg bw.
Changes in V8:
- Adjust ICC vote per transfer, in multimessage transfer scenario.
- Move ICC voting to common API "geni_spi_set_clock_and_bw".
drivers/spi/spi-geni-qcom.c | 36 ++++++++++++++++++++++++++++++++----
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index f186906..7a2e579 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -192,7 +192,8 @@ static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
writel(word_len, se->base + SE_SPI_WORD_LEN);
}
-static int geni_spi_set_clock(struct spi_geni_master *mas, unsigned long clk_hz)
+static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
+ unsigned long clk_hz)
{
u32 clk_sel, m_clk_cfg, idx, div;
struct geni_se *se = &mas->se;
@@ -218,6 +219,12 @@ static int geni_spi_set_clock(struct spi_geni_master *mas, unsigned long clk_hz)
writel(clk_sel, se->base + SE_GENI_CLK_SEL);
writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
+ /* Set BW quota for CPU as driver supports FIFO mode only. */
+ se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
+ ret = geni_icc_set_bw(se);
+ if (ret)
+ return ret;
+
return 0;
}
@@ -259,7 +266,7 @@ static int setup_fifo_params(struct spi_device *spi_slv,
writel(cpol, se->base + SE_SPI_CPOL);
writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
- return geni_spi_set_clock(mas, spi_slv->max_speed_hz);
+ return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
}
static int spi_geni_prepare_message(struct spi_master *spi,
@@ -346,7 +353,7 @@ static void setup_fifo_xfer(struct spi_transfer *xfer,
/* Speed and bits per word can be overridden per transfer */
if (xfer->speed_hz != mas->cur_speed_hz) {
- ret = geni_spi_set_clock(mas, xfer->speed_hz);
+ ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
if (ret)
return;
}
@@ -620,6 +627,17 @@ static int spi_geni_probe(struct platform_device *pdev)
spin_lock_init(&mas->lock);
pm_runtime_enable(dev);
+ ret = geni_icc_get(&mas->se, NULL);
+ if (ret)
+ goto spi_geni_probe_runtime_disable;
+ /* Set the bus quota to a reasonable value for register access */
+ mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
+ mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
+
+ ret = geni_icc_set_bw(&mas->se);
+ if (ret)
+ goto spi_geni_probe_runtime_disable;
+
ret = spi_geni_init(mas);
if (ret)
goto spi_geni_probe_runtime_disable;
@@ -658,14 +676,24 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
{
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ int ret;
+
+ ret = geni_se_resources_off(&mas->se);
+ if (ret)
+ return ret;
- return geni_se_resources_off(&mas->se);
+ return geni_icc_disable(&mas->se);
}
static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
{
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ int ret;
+
+ ret = geni_icc_enable(&mas->se);
+ if (ret)
+ return ret;
return geni_se_resources_on(&mas->se);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH V8 6/8] spi: spi-geni-qcom: Add interconnect support
2020-06-23 10:38 ` [PATCH V8 6/8] spi: spi-geni-qcom: Add interconnect support Akash Asthana
@ 2020-06-23 10:57 ` Mark Brown
0 siblings, 0 replies; 13+ messages in thread
From: Mark Brown @ 2020-06-23 10:57 UTC (permalink / raw)
To: Akash Asthana
Cc: gregkh, agross, bjorn.andersson, wsa, linux-i2c, linux-spi,
devicetree, swboyd, mgautam, linux-arm-msm, linux-serial, mka,
dianders, evgreen, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 231 bytes --]
On Tue, Jun 23, 2020 at 04:08:55PM +0530, Akash Asthana wrote:
> Get the interconnect paths for SPI based Serial Engine device
> and vote according to the current bus speed of the driver.
Acked-by: Mark Brown <broonie@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V8 7/8] spi: spi-qcom-qspi: Add interconnect support
2020-06-23 10:38 [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana
` (5 preceding siblings ...)
2020-06-23 10:38 ` [PATCH V8 6/8] spi: spi-geni-qcom: Add interconnect support Akash Asthana
@ 2020-06-23 10:38 ` Akash Asthana
2020-06-23 10:57 ` Mark Brown
2020-06-23 10:38 ` [PATCH V8 8/8] arm64: dts: sc7180: Add interconnect for QUP and QSPI Akash Asthana
2020-06-25 4:57 ` [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Bjorn Andersson
8 siblings, 1 reply; 13+ messages in thread
From: Akash Asthana @ 2020-06-23 10:38 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, evgreen, linux-kernel, Akash Asthana
Get the interconnect paths for QSPI device and vote according to the
current bus speed of the driver.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
Changes in V2:
- As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
path handle
- As per Matthias comment, added error handling for icc_set_bw call
Changes in V3:
- No Change.
Changes in V4:
- As per Mark's comment move peak_bw guess as twice of avg_bw if
nothing mentioned explicitly to ICC core.
Changes in V5:
- Add icc_enable/disable to power on/off call.
- Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw
from probe so that when resume/icc_enable is called NOC are running at
some non-zero value.
Changes in V6:
- As per Matthias's comment made print statement consistent across driver
Changes in V7:
- As per Matthias's comment removed usage of peak_bw variable because we don't
have explicit peak requirement, we were voting peak = avg and this can be
tracked using single variable for avg bw.
- As per Matthias's comment improved print log.
Changes in Resend V7:
- As per Matthias comment removed "unsigned int avg_bw_cpu" from
struct qcom_qspi as we are using that variable only once.
Changes in V8:
- No change
drivers/spi/spi-qcom-qspi.c | 56 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c
index 3c4f83b..b5b4cf6 100644
--- a/drivers/spi/spi-qcom-qspi.c
+++ b/drivers/spi/spi-qcom-qspi.c
@@ -2,6 +2,7 @@
// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
#include <linux/clk.h>
+#include <linux/interconnect.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
@@ -139,7 +140,8 @@ struct qcom_qspi {
struct device *dev;
struct clk_bulk_data *clks;
struct qspi_xfer xfer;
- /* Lock to protect xfer and IRQ accessed registers */
+ struct icc_path *icc_path_cpu_to_qspi;
+ /* Lock to protect data accessed by IRQs */
spinlock_t lock;
};
@@ -229,6 +231,7 @@ static int qcom_qspi_transfer_one(struct spi_master *master,
int ret;
unsigned long speed_hz;
unsigned long flags;
+ unsigned int avg_bw_cpu;
speed_hz = slv->max_speed_hz;
if (xfer->speed_hz)
@@ -241,6 +244,18 @@ static int qcom_qspi_transfer_one(struct spi_master *master,
return ret;
}
+ /*
+ * Set BW quota for CPU as driver supports FIFO mode only.
+ * We don't have explicit peak requirement so keep it equal to avg_bw.
+ */
+ avg_bw_cpu = Bps_to_icc(speed_hz);
+ ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, avg_bw_cpu, avg_bw_cpu);
+ if (ret) {
+ dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
spin_lock_irqsave(&ctrl->lock, flags);
/* We are half duplex, so either rx or tx will be set */
@@ -458,6 +473,29 @@ static int qcom_qspi_probe(struct platform_device *pdev)
if (ret)
goto exit_probe_master_put;
+ ctrl->icc_path_cpu_to_qspi = devm_of_icc_get(dev, "qspi-config");
+ if (IS_ERR(ctrl->icc_path_cpu_to_qspi)) {
+ ret = PTR_ERR(ctrl->icc_path_cpu_to_qspi);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to get cpu path: %d\n", ret);
+ goto exit_probe_master_put;
+ }
+ /* Set BW vote for register access */
+ ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, Bps_to_icc(1000),
+ Bps_to_icc(1000));
+ if (ret) {
+ dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu: %d\n",
+ __func__, ret);
+ goto exit_probe_master_put;
+ }
+
+ ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
+ if (ret) {
+ dev_err(ctrl->dev, "%s: ICC disable failed for cpu: %d\n",
+ __func__, ret);
+ goto exit_probe_master_put;
+ }
+
ret = platform_get_irq(pdev, 0);
if (ret < 0)
goto exit_probe_master_put;
@@ -511,9 +549,17 @@ static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
+ int ret;
clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks);
+ ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
+ if (ret) {
+ dev_err_ratelimited(ctrl->dev, "%s: ICC disable failed for cpu: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
return 0;
}
@@ -521,6 +567,14 @@ static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
+ int ret;
+
+ ret = icc_enable(ctrl->icc_path_cpu_to_qspi);
+ if (ret) {
+ dev_err_ratelimited(ctrl->dev, "%s: ICC enable failed for cpu: %d\n",
+ __func__, ret);
+ return ret;
+ }
return clk_bulk_prepare_enable(QSPI_NUM_CLKS, ctrl->clks);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH V8 7/8] spi: spi-qcom-qspi: Add interconnect support
2020-06-23 10:38 ` [PATCH V8 7/8] spi: spi-qcom-qspi: " Akash Asthana
@ 2020-06-23 10:57 ` Mark Brown
0 siblings, 0 replies; 13+ messages in thread
From: Mark Brown @ 2020-06-23 10:57 UTC (permalink / raw)
To: Akash Asthana
Cc: gregkh, agross, bjorn.andersson, wsa, linux-i2c, linux-spi,
devicetree, swboyd, mgautam, linux-arm-msm, linux-serial, mka,
dianders, evgreen, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 212 bytes --]
On Tue, Jun 23, 2020 at 04:08:56PM +0530, Akash Asthana wrote:
> Get the interconnect paths for QSPI device and vote according to the
> current bus speed of the driver.
Acked-by: Mark Brown <broonie@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V8 8/8] arm64: dts: sc7180: Add interconnect for QUP and QSPI
2020-06-23 10:38 [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana
` (6 preceding siblings ...)
2020-06-23 10:38 ` [PATCH V8 7/8] spi: spi-qcom-qspi: " Akash Asthana
@ 2020-06-23 10:38 ` Akash Asthana
2020-06-25 4:57 ` [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Bjorn Andersson
8 siblings, 0 replies; 13+ messages in thread
From: Akash Asthana @ 2020-06-23 10:38 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, evgreen, linux-kernel, Akash Asthana
Add interconnect ports for GENI QUPs and QSPI to set bus capabilities.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
---
Changes in V2:
- As per Bjorn's comment, ignoring 80 char limit in defining interconnects
paths.
Changes in V3:
- No change.
Change in V4:
- No change.
Changes in V5:
- No change.
Chnages in V6:
- No change.
Changes in V7:
- No change.
Changes in V8:
- No change.
arch/arm64/boot/dts/qcom/sc7180.dtsi | 127 +++++++++++++++++++++++++++++++++++
1 file changed, 127 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 3a8076c..ad57df2 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -547,6 +547,8 @@
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x43 0x0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>;
+ interconnect-names = "qup-core";
status = "disabled";
i2c0: i2c@880000 {
@@ -559,6 +561,11 @@
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -572,6 +579,9 @@
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -583,6 +593,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -596,6 +609,11 @@
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -609,6 +627,9 @@
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -620,6 +641,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -633,6 +657,11 @@
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -644,6 +673,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -657,6 +689,11 @@
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -670,6 +707,9 @@
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -681,6 +721,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -694,6 +737,11 @@
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -705,6 +753,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -718,6 +769,11 @@
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -731,6 +787,9 @@
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -742,6 +801,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
@@ -756,6 +818,8 @@
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x4c3 0x0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>;
+ interconnect-names = "qup-core";
status = "disabled";
i2c6: i2c@a80000 {
@@ -768,6 +832,11 @@
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -781,6 +850,9 @@
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -792,6 +864,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart6_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -805,6 +880,11 @@
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -816,6 +896,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -829,6 +912,11 @@
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -842,6 +930,9 @@
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -853,6 +944,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart8_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -866,6 +960,11 @@
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -877,6 +976,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -890,6 +992,11 @@
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -903,6 +1010,9 @@
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -914,6 +1024,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart10_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -927,6 +1040,11 @@
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -940,6 +1058,9 @@
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -951,6 +1072,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart11_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
@@ -2132,6 +2256,9 @@
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>;
clock-names = "iface", "core";
+ interconnects = <&gem_noc MASTER_APPSS_PROC
+ &config_noc SLAVE_QSPI_0>;
+ interconnect-names = "qspi-config";
status = "disabled";
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers
2020-06-23 10:38 [PATCH V8 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana
` (7 preceding siblings ...)
2020-06-23 10:38 ` [PATCH V8 8/8] arm64: dts: sc7180: Add interconnect for QUP and QSPI Akash Asthana
@ 2020-06-25 4:57 ` Bjorn Andersson
8 siblings, 0 replies; 13+ messages in thread
From: Bjorn Andersson @ 2020-06-25 4:57 UTC (permalink / raw)
To: Akash Asthana
Cc: gregkh, agross, wsa, broonie, linux-i2c, linux-spi, devicetree,
swboyd, mgautam, linux-arm-msm, linux-serial, mka, dianders,
evgreen, linux-kernel
On Tue 23 Jun 03:38 PDT 2020, Akash Asthana wrote:
> This patch series is based on tag "next-20200622" of linux-next tree.
>
Series applied to the qcom tree, thank you and thanks for the Acks.
Regards,
Bjorn
> High level design:
> - QUP wrapper/common driver.
> Vote for QUP core on behalf of earlycon from probe.
> Remove BW vote during earlycon exit call
>
> - SERIAL driver.
> Vote only for CPU/CORE path because driver is in FIFO mode only
> Vote/unvote from qcom_geni_serial_pm func.
> Bump up the CPU vote from set_termios call based on real time need
>
> - I2C driver.
> Vote for CORE/CPU/DDR path
> Vote/unvote from runtime resume/suspend callback
> As bus speed for I2C is fixed from probe itself no need for bump up.
>
> - SPI QUP driver.
> Vote only for CPU/CORE path because driver is in FIFO mode only
> Vote/unvote from runtime resume/suspend callback
> Bump up CPU vote based on real time need per transfer.
>
> - QSPI driver.
> Vote only for CPU path
> Vote/unvote from runtime resume/suspend callback
> Bump up CPU vote based on real time need per transfer.
>
> Changes in V2:
> - Add devm_of_icc_get() API interconnect core.
> - Add ICC support to common driver to fix earlyconsole crash.
>
> Changes in V3:
> - Define common ICC APIs in geni-se driver and use it across geni based
> I2C,SPI and UART driver.
>
> Changes in V4:
> - Add a patch to ICC core to scale peak requirement
> as twice of average if it is not mentioned explicilty.
>
> Changes in V5:
> - As per Georgi's suggestion removed patch from ICC core for assuming
> peak_bw as twice of average when it's not mentioned, instead assume it
> equall to avg_bw and keep this assumption in ICC client itself.
> - As per Matthias suggestion use enum for GENI QUP ICC paths.
>
> Changes in V6:
> - No Major change
>
> Changes in V7:
> - As per Matthias's comment removed usage of peak_bw variable because we don't
> have explicit peak requirement, we were voting peak = avg and this can be
> tracked using single variable for avg bw.
> - As per Matthias's comment improved print log.
>
> Changes in V8:
> - Add [PATCH V8 5/8] to factor out common code for clock setting.
> - Combine ICC voting and clock setting to single API. [PATCH V8 6/8]
> - Add ICC voting per transfer because in case of multi message,
> transfer frequency can vary for each message/transfer.[PATCH V8 6/8]
>
> Akash Asthana (7):
> soc: qcom: geni: Support for ICC voting
> soc: qcom-geni-se: Add interconnect support to fix earlycon crash
> i2c: i2c-qcom-geni: Add interconnect support
> tty: serial: qcom_geni_serial: Add interconnect support
> spi: spi-geni-qcom: Add interconnect support
> spi: spi-qcom-qspi: Add interconnect support
> arm64: dts: sc7180: Add interconnect for QUP and QSPI
>
> Douglas Anderson (1):
> spi: spi-geni-qcom: Combine the clock setting code
>
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 127 ++++++++++++++++++++++++++++
> drivers/i2c/busses/i2c-qcom-geni.c | 26 +++++-
> drivers/soc/qcom/qcom-geni-se.c | 150 ++++++++++++++++++++++++++++++++++
> drivers/spi/spi-geni-qcom.c | 100 +++++++++++++++--------
> drivers/spi/spi-qcom-qspi.c | 56 ++++++++++++-
> drivers/tty/serial/qcom_geni_serial.c | 38 ++++++++-
> include/linux/qcom-geni-se.h | 40 +++++++++
> 7 files changed, 496 insertions(+), 41 deletions(-)
>
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
>
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