Re: [PATCH 3/8] soc: samsung: Add USIv2 driver

Krzysztof Kozlowski
2021-11-29T08:51:34Z

On 27/11/2021 23:32, Sam Protsenko wrote:
> USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and
> provides selectable serial protocol (one of: UART, SPI, I2C). USIv2
> registers usually reside in the same register map as a particular
> underlying protocol it implements, but have some particular offset. E.g.
> on Exynos850 the USI_UART has 0x13820000 base address, where UART
> registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc
> offsets. Desired protocol can be chosen via SW_CONF register from System
> Register block of the same domain as USI.
>
> Before starting to use a particular protocol, USIv2 must be configured
> properly:
> 1. Select protocol to be used via System Register
> 2. Clear "reset" flag in USI_CON
> 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be
> disabled, so that the IP clock is not gated automatically); this is
> done using USI_OPTION register
> 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers
> modification
>
> This driver implements above behavior. Of course, USIv2 driver should be
> probed before UART/I2C/SPI drivers. It can be achived by embedding
> UART/I2C/SPI nodes inside of USI node (in Device Tree); driver then
> walks underlying nodes and instantiates those. Driver also handles USI
> configuration on PM resume, as register contents can be lost during CPU
> suspend.
>
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> ---
> drivers/soc/samsung/Kconfig | 14 ++
> drivers/soc/samsung/Makefile | 2 +
> drivers/soc/samsung/exynos-usi-v2.c | 242 ++++++++++++++++++++++++++++

You used everywhere v2 naming, but I actually hope this driver will be
able to support also v1 and vx of USI. IOW, I expect to have only one
USI driver, so please drop everywhere v2 (bindings, symbols, Kconfig,
functions) except the compatible.

> 3 files changed, 258 insertions(+)
> create mode 100644 drivers/soc/samsung/exynos-usi-v2.c
>
> diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig
> index e2cedef1e8d1..b168973c887f 100644
> --- a/drivers/soc/samsung/Kconfig
> +++ b/drivers/soc/samsung/Kconfig
> @@ -23,6 +23,20 @@ config EXYNOS_CHIPID
> Support for Samsung Exynos SoC ChipID and Adaptive Supply Voltage.
> This driver can also be built as module (exynos_chipid).
>
> +config EXYNOS_USI_V2
> + tristate "Exynos USIv2 (Universal Serial Interface) driver"
> + default ARCH_EXYNOS && ARM64
> + depends on ARCH_EXYNOS || COMPILE_TEST
> + select MFD_SYSCON
> + help
> + Enable support for USIv2 block. USI (Universal Serial Interface) is an
> + IP-core found in modern Samsung Exynos SoCs, like Exynos850 and
> + ExynosAutoV0. USI block can be configured to provide one of the
> + following serial protocols: UART, SPI or High Speed I2C.
> +
> + This driver allows one to configure USI for desired protocol, which
> + is usually done in USI node in Device Tree.
> +
> config EXYNOS_PMU
> bool "Exynos PMU controller driver" if COMPILE_TEST
> depends on ARCH_EXYNOS || ((ARM || ARM64) && COMPILE_TEST)
> diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
> index 2ae4bea804cf..0b746b2fd78f 100644
> --- a/drivers/soc/samsung/Makefile
> +++ b/drivers/soc/samsung/Makefile
> @@ -4,6 +4,8 @@ obj-$(CONFIG_EXYNOS_ASV_ARM) += exynos5422-asv.o
> obj-$(CONFIG_EXYNOS_CHIPID) += exynos_chipid.o
> exynos_chipid-y += exynos-chipid.o exynos-asv.o
>
> +obj-$(CONFIG_EXYNOS_USI_V2) += exynos-usi-v2.o
> +
> obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o
>
> obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \
> diff --git a/drivers/soc/samsung/exynos-usi-v2.c b/drivers/soc/samsung/exynos-usi-v2.c
> new file mode 100644
> index 000000000000..5a315890e4ec
> --- /dev/null
> +++ b/drivers/soc/samsung/exynos-usi-v2.c
> @@ -0,0 +1,242 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 Linaro Ltd.
> + * Author: Sam Protsenko <semen.protsenko@linaro.org>
> + *
> + * Samsung Exynos USI v2 driver (Universal Serial Interface).
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +
> +#include <dt-bindings/soc/samsung,exynos-usi-v2.h>
> +
> +/* System Register: SW_CONF register bits */
> +#define SW_CONF_UART BIT(0)
> +#define SW_CONF_SPI BIT(1)
> +#define SW_CONF_I2C BIT(2)
> +#define SW_CONF_MASK (SW_CONF_UART | SW_CONF_SPI | SW_CONF_I2C)
> +
> +/* USI register offsets */
> +#define USI_CON 0x04
> +#define USI_OPTION 0x08
> +
> +/* USI register bits */
> +#define USI_CON_RESET BIT(0)
> +#define USI_OPTION_CLKREQ_ON BIT(1)
> +#define USI_OPTION_CLKSTOP_ON BIT(2)
> +
> +struct usi_v2_mode {

Everywhere here:
s/usi_v2/exynos_usi/

> + const char *name; /* mode name */
> + unsigned int val; /* mode register value */
> +};
> +
> +struct usi_v2 {
> + struct device *dev;> + void __iomem *regs; /* USI register map */
> + struct clk *pclk; /* USI bus clock */
> + struct clk *ipclk; /* USI operating clock */
> +
> + size_t mode; /* current USI SW_CONF mode index */
> + bool clkreq_on; /* always provide clock to IP */
> +
> + /* System Register */
> + struct regmap *sysreg; /* System Register map */
> + unsigned int sw_conf; /* SW_CONF register offset in sysreg */
> +};
> +
> +static const struct usi_v2_mode usi_v2_modes[] = {
> + [USI_V2_UART] = { .name = "uart", .val = SW_CONF_UART },
> + [USI_V2_SPI] = { .name = "spi", .val = SW_CONF_SPI },
> + [USI_V2_I2C] = { .name = "i2c", .val = SW_CONF_I2C },
> +};
> +
> +/**
> + * usi_v2_set_sw_conf - Set USI block configuration mode
> + * @usi: USI driver object
> + * @mode: Mode index
> + *
> + * Select underlying serial protocol (UART/SPI/I2C) in USI IP-core.
> + *
> + * Return: 0 on success, or negative error code on failure.
> + */
> +static int usi_v2_set_sw_conf(struct usi_v2 *usi, size_t mode)
> +{
> + unsigned int val;
> + int ret;
> +
> + if (mode >= ARRAY_SIZE(usi_v2_modes))
> + return -EINVAL;
> +
> + val = usi_v2_modes[mode].val;
> + ret = regmap_update_bits(usi->sysreg, usi->sw_conf, SW_CONF_MASK, val);
> + if (ret)
> + return ret;
> +
> + usi->mode = mode;
> + dev_dbg(usi->dev, "USIv2 protocol: %s\n", usi_v2_modes[usi->mode].name);
> +
> + return 0;
> +}
> +
> +/**
> + * usi_v2_enable - Initialize USI block
> + * @usi: USI driver object
> + *
> + * USI IP-core start state is "reset" (on startup and after CPU resume). This
> + * routine enables USI block by clearing the reset flag. It also configures
> + * HWACG behavior (needed e.g. for UART Rx). It should be performed before
> + * underlying protocol becomes functional.
> + *
> + * Both 'pclk' and 'ipclk' clocks should be enabled when running this function.
> + */
> +static void usi_v2_enable(const struct usi_v2 *usi)
> +{
> + u32 val;
> +
> + /* Enable USI block */
> + val = readl(usi->regs + USI_CON);
> + val &= ~USI_CON_RESET;
> + writel(val, usi->regs + USI_CON);
> + udelay(1);
> +
> + /* Continuously provide the clock to USI IP w/o gating */
> + if (usi->clkreq_on) {
> + val = readl(usi->regs + USI_OPTION);
> + val &= ~USI_OPTION_CLKSTOP_ON;
> + val |= USI_OPTION_CLKREQ_ON;
> + writel(val, usi->regs + USI_OPTION);
> + }
> +}
> +
> +static int usi_v2_configure(struct usi_v2 *usi)
> +{
> + int ret;
> +
> + ret = clk_prepare_enable(usi->pclk);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(usi->ipclk);
> + if (ret)
> + goto err_pclk;
> +
> + ret = usi_v2_set_sw_conf(usi, usi->mode);
> + if (ret)
> + goto err_ipclk;
> +
> + usi_v2_enable(usi);
> +
> +err_ipclk:
> + clk_disable_unprepare(usi->ipclk);
> +err_pclk:
> + clk_disable_unprepare(usi->pclk);
> + return ret;
> +}
> +
> +static int usi_v2_parse_dt(struct device_node *np, struct usi_v2 *usi)
> +{
> + int ret;
> + u32 mode;
> +
> + ret = of_property_read_u32(np, "samsung,mode", &mode);
> + if (ret)
> + return ret;
> + usi->mode = mode;

Parse and validate mode here, instead of usi_v2_set_sw_conf(). We expect
DT to be correct, so if it is not, then there is no point to probe the
device.

Best regards,
Krzysztof