[PATCH 18/64] i2c: eg20t: reword according to newest specification

Wolfram Sang
2024-03-22T13:26:52Z

drivers/i2c/busses/i2c-eg20t.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/i2c/busses/i2c-eg20t.c b/drivers/i2c/busses/i2c-eg20t.c
index 4914bfbee2a9..e95793036f5d 100644
--- a/drivers/i2c/busses/i2c-eg20t.c
+++ b/drivers/i2c/busses/i2c-eg20t.c
@@ -337,7 +337,7 @@ static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
adap->pch_event_flag = 0;

if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
- pch_dbg(adap, "Receive NACK for slave address setting\n");
+ pch_dbg(adap, "Receive NACK for client address setting\n");
return -ENXIO;
}

@@ -382,7 +382,7 @@ static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
buf = msgs->buf;
addr = msgs->addr;

- /* enable master tx */
+ /* enable host tx */
pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);

pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
@@ -406,7 +406,7 @@ static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
addr_8_lsb = (addr & I2C_ADDR_MSK);
iowrite32(addr_8_lsb, p + PCH_I2CDR);
} else {
- /* set 7 bit slave address and R/W bit as 0 */
+ /* set 7 bit client address and R/W bit as 0 */
iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
if (first)
pch_i2c_start(adap);
@@ -500,7 +500,7 @@ static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
buf = msgs->buf;
addr = msgs->addr;

- /* enable master reception */
+ /* enable host reception */
pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);

if (first) {
@@ -708,7 +708,7 @@ static u32 pch_i2c_func(struct i2c_adapter *adap)
}

static const struct i2c_algorithm pch_algorithm = {
- .master_xfer = pch_i2c_xfer,
+ .xfer = pch_i2c_xfer,
.functionality = pch_i2c_func
};

--
2.43.0