[PATCH 2/2] dt-bindings: i2c: snps,designware-i2c: add bus-loading and clk-freq-optimized

[Michael Wu <michael.wu@kneron.us>]

Since there are no registers controlling the hardware parameters
IC_CAP_LOADING and IC_CLK_FREQ_OPTIMIZATION, their values can only be
noted in the device tree.

"bus-loading" is used to declare the value of IC_CAP_LOADING, and
"clk-freq-optimized" is used to declare IC_CLK_FREQ_OPTIMIZATION = 1.

Signed-off-by: Michael Wu <michael.wu@kneron.us>
---
 .../bindings/i2c/snps,designware-i2c.yaml     | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
index 60035a787e5c..f954f5014a00 100644
--- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
@@ -87,6 +87,16 @@ properties:
       This value is used to compute the tHIGH period.
     default: 300
 
+  bus-loading:
+    description: |
+      This property should be 100 or 400 for high speed mode.
+      This value is used to compute the tHIGH period and the tLOW period.
+    default: 100
+
+  clk_freq_optimized:
+    description: |
+      Thie property is used to declare whether the internal latency is reduced.
+
   dmas:
     items:
       - description: TX DMA Channel
@@ -146,4 +156,13 @@ examples:
       interrupts = <8>;
       clocks = <&ahb_clk>;
     };
+  - |
+    i2c@ce500000 {
+      compatible = "snps,designware-i2c";
+      reg = <0xce500000 0x1000>;
+      interrupts = <37 1>;
+      clock-frequency = <3400000>;
+      bus-loading = <400>;
+      clk-freq-optimized;
+    };
 ...
-- 
2.43.0