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Thu, 24 Jul 2025 22:23:06 -0700 From: Rajesh Gumasta To: , , , , , , , CC: , , , , , , , Rajesh Gumasta Subject: [PATCH V3 1/3] dt-binding: Add register-settings binding Date: Fri, 25 Jul 2025 10:52:23 +0530 Message-ID: <20250725052225.23510-2-rgumasta@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250725052225.23510-1-rgumasta@nvidia.com> References: <20250725052225.23510-1-rgumasta@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003439:EE_|DM3PR12MB9286:EE_ X-MS-Office365-Filtering-Correlation-Id: 58f029d0-3cc6-46aa-a548-08ddcb3b5fcc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024|13003099007; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jul 2025 05:23:22.5957 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58f029d0-3cc6-46aa-a548-08ddcb3b5fcc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003439.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9286 Add a new device-tree binding for a 'reg-settings' node that can be added to any device. This 'reg-settings' is used to populate register settings that need to be programmed for a given operating mode of the device. An example usage of the 'reg-settings' node is shown below for the NVIDIA Tegra MMC controller which needs to program a specific 'num-tuning-iterations' value in a register field for each operating mode: mmc@700b0000 { reg-settings { default-settings { /* Default register setting */ nvidia,num-tuning-iterations = <0>; }; sdr50 { /* SDR50 register setting */ nvidia,num-tuning-iterations = <4>; }; sdr104 { /* SDR104 register setting */ nvidia,num-tuning-iterations = <2>; }; hs200 { /* HS200 register setting */ nvidia,num-tuning-iterations = <2>; }; }; }; The 'reg-settings' child nodes are defined according to the operating modes supported for a given device. Properties within each operating mode are then defined by the bindings for the devices that require them. Signed-off-by: Rajesh Gumasta --- .../bindings/regset/register-settings.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/regset/register-settings.yaml diff --git a/Documentation/devicetree/bindings/regset/register-settings.yaml b/Documentation/devicetree/bindings/regset/register-settings.yaml new file mode 100644 index 000000000000..4366cdd72813 --- /dev/null +++ b/Documentation/devicetree/bindings/regset/register-settings.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regset/register-settings.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Register Settings + +maintainers: + - Thierry Reding + - Krishna Yarlagadda + - Rajesh Gumasta + - Jon Hunter + +description: | + Register Settings provides a generic way to specify register configurations + for any hardware controllers. Settings are specified under a "reg-settings" + sub-node under the controller device tree node. It allows defining both + default and operating mode specific register settings in the device tree. + +properties: + reg-settings: + type: object + description: | + Container node for register settings configurations. Each child node + represents a specific configuration mode or operating condition. + + additionalProperties: + type: object + +additionalProperties: true -- 2.50.1