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Thu, 24 Jul 2025 22:23:12 -0700 From: Rajesh Gumasta To: , , , , , , , CC: , , , , , , , Rajesh Gumasta Subject: [PATCH V3 2/3] dt-binding: i2c: nvidia,tegra20-i2c: Add register-setting support Date: Fri, 25 Jul 2025 10:52:24 +0530 Message-ID: <20250725052225.23510-3-rgumasta@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250725052225.23510-1-rgumasta@nvidia.com> References: <20250725052225.23510-1-rgumasta@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD9:EE_|PH8PR12MB7278:EE_ X-MS-Office365-Filtering-Correlation-Id: 1d2b68e1-b1a1-418a-2484-08ddcb3b656c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|7416014|82310400026|1800799024|13003099007; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jul 2025 05:23:31.9770 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d2b68e1-b1a1-418a-2484-08ddcb3b656c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7278 Add register setting support for the NVIDIA Tegra20 I2C controllers. An i2c-controller-common.yaml binding document has been added a top-level binding document so that all I2C controllers can use this binding. This new binding document defines some generic register setting properties for I2C and some standard I2C operating modes that the register settings need to be programmed for. This new binding document is used by the NVIDIA Tegra20 I2C binding to enable the use of the 'reg-settings' binding for this device. Signed-off-by: Rajesh Gumasta --- .../bindings/i2c/i2c-controller-common.yaml | 73 +++++++++++++++++++ .../bindings/i2c/nvidia,tegra20-i2c.yaml | 64 +++++++++++++++- 2 files changed, 134 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-controller-common.yaml diff --git a/Documentation/devicetree/bindings/i2c/i2c-controller-common.yaml b/Documentation/devicetree/bindings/i2c/i2c-controller-common.yaml new file mode 100644 index 000000000000..3b5b75d4b98a --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-controller-common.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-controller-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: I2C Controller Common Properties + +maintainers: + - Thierry Reding + - Krishna Yarlagadda + - Rajesh Gumasta + - Jon Hunter + +description: + These properties are common to multiple I2C controllers. + +definitions: + reg-settings: + properties: + scl-low-period-cycles: + $ref: /schemas/types.yaml#/definitions/uint8 + description: Low period of the SCL clock in parent clock cycles. + scl-high-period-cycles: + $ref: /schemas/types.yaml#/definitions/uint8 + description: High period of the SCL clock in parent clock cycles. + bus-free-time-cycles: + $ref: /schemas/types.yaml#/definitions/uint8 + description: Bus free time between STOP and START conditions in parent + clock cycles. + start-setup-time-cycles: + $ref: /schemas/types.yaml#/definitions/uint8 + description: Set-up time for START condition in parent clock cycles. + stop-setup-time-cycles: + $ref: /schemas/types.yaml#/definitions/uint8 + description: Set-up time for STOP condition in parent clock cycles. + start-hold-time-cycles: + $ref: /schemas/types.yaml#/definitions/uint8 + description: Hold time for STOP condition in parent clock cycles. + +properties: + reg-settings: + $ref: /schemas/regset/register-settings.yaml + + properties: + default-setting: + type: object + $ref: "#/definitions/reg-settings" + description: + Default register settings. + + fast: + type: object + $ref: "#/definitions/reg-settings" + description: + Register settings for I2C fast operating mode. + + fastplus: + type: object + $ref: "#/definitions/reg-settings" + description: + Register settings for I2C fastplus operating mode. + + standard: + type: object + $ref: "#/definitions/reg-settings" + description: + Register settings for I2C standard operating mode. + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml index 6b6f6762d122..695ce5ada7d5 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml @@ -119,6 +119,28 @@ properties: - const: rx - const: tx + reg-settings: + $ref: /schemas/i2c/i2c-controller-common.yaml#/properties/reg-settings + + properties: + default-setting: + $ref: /schemas/i2c/i2c-controller-common.yaml#/definitions/reg-settings + unevaluatedProperties: false + + fast: + $ref: /schemas/i2c/i2c-controller-common.yaml#/definitions/reg-settings + unevaluatedProperties: false + + fastplus: + $ref: /schemas/i2c/i2c-controller-common.yaml#/definitions/reg-settings + unevaluatedProperties: false + + standard: + $ref: /schemas/i2c/i2c-controller-common.yaml#/definitions/reg-settings + unevaluatedProperties: false + + unevaluatedProperties: false + required: - compatible - reg @@ -127,7 +149,7 @@ required: - clock-names allOf: - - $ref: /schemas/i2c/i2c-controller.yaml + - $ref: /schemas/i2c/i2c-controller-common.yaml - if: properties: compatible: @@ -206,6 +228,42 @@ examples: dmas = <&apbdma 16>, <&apbdma 16>; dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; + i2c-bus { + #address-cells = <1>; + #size-cells = <0>; + }; + + reg-settings { + default-setting { + scl-high-period-cycles = /bits/ 8 <3>; + scl-low-period-cycles = /bits/ 8 <8>; + }; + + fast { + scl-high-period-cycles = /bits/ 8 <2>; + scl-low-period-cycles = /bits/ 8 <2>; + bus-free-time-cycles = /bits/ 8 <2>; + stop-setup-time-cycles = /bits/ 8 <2>; + start-hold-time-cycles = /bits/ 8 <2>; + start-setup-time-cycles = /bits/ 8 <2>; + }; + + fastplus { + scl-high-period-cycles = /bits/ 8 <2>; + scl-low-period-cycles = /bits/ 8 <2>; + bus-free-time-cycles = /bits/ 8 <2>; + stop-setup-time-cycles = /bits/ 8 <2>; + start-hold-time-cycles = /bits/ 8 <2>; + start-setup-time-cycles = /bits/ 8 <2>; + }; + + standard { + scl-high-period-cycles = /bits/ 8 <7>; + scl-low-period-cycles = /bits/ 8 <8>; + bus-free-time-cycles = /bits/ 8 <8>; + stop-setup-time-cycles = /bits/ 8 <8>; + start-hold-time-cycles = /bits/ 8 <8>; + start-setup-time-cycles = /bits/ 8 <8>; + }; + }; }; -- 2.50.1