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Thu, 24 Jul 2025 22:23:17 -0700 From: Rajesh Gumasta To: , , , , , , , CC: , , , , , , , Rajesh Gumasta Subject: [PATCH V3 3/3] dt-binding: mmc: tegra: Add register-setting support Date: Fri, 25 Jul 2025 10:52:25 +0530 Message-ID: <20250725052225.23510-4-rgumasta@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250725052225.23510-1-rgumasta@nvidia.com> References: <20250725052225.23510-1-rgumasta@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD9:EE_|PH0PR12MB7472:EE_ X-MS-Office365-Filtering-Correlation-Id: 34c07602-fc65-41db-98be-08ddcb3b685b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jul 2025 05:23:36.8722 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34c07602-fc65-41db-98be-08ddcb3b685b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7472 Add register setting support for the NVIDIA Tegra20 MMC controllers. The top-level 'reg-settings' node and child nodes for each MMC operating mode supported are defined in the mmc-controller-common.yaml binding. The NVIDIA specific register setting property is defined in the nvidia,tegra20-sdhci.yaml. Signed-off-by: Rajesh Gumasta --- .../bindings/mmc/mmc-controller-common.yaml | 24 ++++++++++ .../bindings/mmc/nvidia,tegra20-sdhci.yaml | 48 +++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml index 9a7235439759..0bdebc6454d8 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml @@ -308,6 +308,30 @@ properties: sequence. To successfully detect an (e)MMC/SD/SDIO card, that power sequence must be maintained while initializing the card. + reg-settings: + $ref: /schemas/regset/register-settings.yaml + + properties: + default-settings: + type: object + description: + Default MMC register settings. + + sdr50: + type: object + description: + Register settings for MMC sdr50 operating mode. + + sdr104: + type: object + description: + Register settings for MMC sdr104 operating mode. + + hs200: + type: object + description: + Register settings for MMC hs200 operating mode. + patternProperties: "^.*@[0-9]+$": type: object diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml index 72987f0326a1..a78b2bd92b18 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -17,6 +17,15 @@ description: | This file documents differences between the core properties described by mmc-controller.yaml and the properties for the Tegra SDHCI controller. +definitions: + reg-settings: + properties: + nvidia,num-tuning-iterations: + description: The number of tuning iterations to be used by tuning circuit. + $ref: /schemas/types.yaml#/definitions/uint8 + minimum: 0 + maximum: 4 + properties: compatible: oneOf: @@ -177,6 +186,27 @@ properties: operates at a 1.8 V fixed I/O voltage. $ref: /schemas/types.yaml#/definitions/flag + reg-settings: + $ref: /schemas/mmc/mmc-controller-common.yaml#/properties/reg-settings + + properties: + default-settings: + $ref: "#/definitions/reg-settings" + unevaluatedProperties: false + + sdr50: + $ref: "#/definitions/reg-settings" + unevaluatedProperties: false + + sdr104: + $ref: "#/definitions/reg-settings" + unevaluatedProperties: false + + hs200: + $ref: "#/definitions/reg-settings" + unevaluatedProperties: false + unevaluatedProperties: false + required: - compatible - reg @@ -310,4 +340,22 @@ examples: <&tegra_car TEGRA210_CLK_PLL_C4>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; + + reg-settings { + default-settings { + nvidia,num-tuning-iterations = /bits/ 8 <0>; + }; + + sdr50 { + nvidia,num-tuning-iterations = /bits/ 8 <4>; + }; + + sdr104 { + nvidia,num-tuning-iterations = /bits/ 8 <2>; + }; + + hs200 { + nvidia,num-tuning-iterations = /bits/ 8 <2>; + }; + }; }; -- 2.50.1