[PATCH RESEND v1 i2c-master] i2c: mchp-pci1xxxx: PCIe Hot reset disable support for Rev C0+ devices

[PATCH RESEND v1 i2c-master] i2c: mchp-pci1xxxx: PCIe Hot reset disable support for Rev C0+ devices

[Rengarajan S]

Systems that issue PCIe hot reset requests during a suspend/resume
cycle cause PCI1XXXX device revisions prior to C0 to get its SMBUS
controller registers reset to hardware default values. This results
in device inaccessibility and I2C read/write failure. Starting with
Revision C0, support was added in the device hardware (via the Hot
Reset Disable Bit) to allow resetting only the PCIe interface and its
associated logic, but preserving the SMBUS registers during a hot
reset. This patch enables the hot reset disable feature during suspend/
resume for C0 and later revisions of the device.

Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
---
 drivers/i2c/busses/i2c-mchp-pci1xxxx.c | 38 ++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/i2c/busses/i2c-mchp-pci1xxxx.c b/drivers/i2c/busses/i2c-mchp-pci1xxxx.c
index cb9455b38c1d..797ccac8b339 100644
--- a/drivers/i2c/busses/i2c-mchp-pci1xxxx.c
+++ b/drivers/i2c/busses/i2c-mchp-pci1xxxx.c
@@ -21,6 +21,7 @@
 
 #define SMBUS_MAST_CORE_ADDR_BASE		0x00000
 #define SMBUS_MAST_SYS_REG_ADDR_BASE		0x01000
+#define CONFIG_REG_ADDR_BASE			0x00000
 
 /* SMB register space. */
 #define SMB_CORE_CTRL_REG_OFF	(SMBUS_MAST_CORE_ADDR_BASE + 0x00)
@@ -300,6 +301,7 @@
 #define SMBUS_RESET_REG		(SMBUS_MAST_CORE_ADDR_BASE + 0x248)
 
 #define PERI_SMBUS_D3_RESET_DIS		BIT(16)
+#define PERI_SMBUS_HOT_RESET_DIS	BIT(17)
 
 #define SMBUS_MST_BUF		(SMBUS_MAST_CORE_ADDR_BASE + 0x280)
 
@@ -316,6 +318,14 @@
 #define SMB_GPR_REG		(SMBUS_MAST_CORE_ADDR_BASE + 0x1000 + 0x0c00 + \
 				0x00)
 
+/* Device Revision Register. */
+#define SMB_GPR_DEV_REV_REG	(SMBUS_MAST_CORE_ADDR_BASE + \
+				 SMBUS_MAST_SYS_REG_ADDR_BASE + \
+				 CONFIG_REG_ADDR_BASE + \
+				 0x0000)
+
+#define SMB_GPR_DEV_REV_MASK	GENMASK(7, 0)
+
 /* Lock Register. */
 #define SMB_GPR_LOCK_REG	(SMBUS_MAST_CORE_ADDR_BASE + 0x1000 + 0x0000 + \
 				0x00A0)
@@ -327,6 +337,7 @@ struct pci1xxxx_i2c {
 	bool i2c_xfer_in_progress;
 	struct i2c_adapter adap;
 	void __iomem *i2c_base;
+	u32 dev_rev;
 	u32 freq;
 	u32 flags;
 };
@@ -1086,6 +1097,8 @@ static int pci1xxxx_i2c_suspend(struct device *dev)
 	 * registers.
 	 */
 	regval = readl(p);
+	if (i2c->dev_rev >= 0xC0)
+		regval |= PERI_SMBUS_HOT_RESET_DIS;
 	regval |= PERI_SMBUS_D3_RESET_DIS;
 	writel(regval, p);
 
@@ -1108,6 +1121,8 @@ static int pci1xxxx_i2c_resume(struct device *dev)
 	writew(regval, p1);
 	pci1xxxx_i2c_config_high_level_intr(i2c, SMBALERT_WAKE_INTR_MASK, false);
 	regval = readl(p2);
+	if (i2c->dev_rev >= 0xC0)
+		regval &= ~PERI_SMBUS_HOT_RESET_DIS;
 	regval &= ~PERI_SMBUS_D3_RESET_DIS;
 	writel(regval, p2);
 	i2c_mark_adapter_resumed(&i2c->adap);
@@ -1126,6 +1141,25 @@ static void pci1xxxx_i2c_shutdown(void *data)
 	pci1xxxx_i2c_configure_core_reg(i2c, false);
 }
 
+static int pci1xxxx_i2c_get_device_revision(struct pci1xxxx_i2c *i2c)
+{
+	void __iomem *p = i2c->i2c_base + SMB_GPR_DEV_REV_REG;
+	u32 regval;
+	int ret;
+
+	ret = set_sys_lock(i2c);
+
+	if (ret)
+		return ret;
+
+	regval = readl(p);
+	i2c->dev_rev = regval & SMB_GPR_DEV_REV_MASK;
+
+	release_sys_lock(i2c);
+
+	return ret;
+}
+
 static int pci1xxxx_i2c_probe_pci(struct pci_dev *pdev,
 				  const struct pci_device_id *ent)
 {
@@ -1158,6 +1192,10 @@ static int pci1xxxx_i2c_probe_pci(struct pci_dev *pdev,
 	init_completion(&i2c->i2c_xfer_done);
 	pci1xxxx_i2c_init(i2c);
 
+	ret = pci1xxxx_i2c_get_device_revision(i2c);
+	if (ret)
+		return ret;
+
 	ret = devm_add_action(dev, pci1xxxx_i2c_shutdown, i2c);
 	if (ret)
 		return ret;
-- 
2.25.1

[PATCH RESEND v1 i2c-master] i2c: mchp-pci1xxxx: Update minimum bus idle time

[Rengarajan S]

The SMBUS controller clock is designed with a 64 MHz clock for the
MCU, while the PCI1xxxx chip assumes a 31.25 MHz baud clock. SMBUS
controller register values are calculated considering 1 unit = 32 ns.
Based on this unit, the BUS_IDLE_MIN register values are updated for
all supported clock frequencies. Setting the MSB of BUS_IDLE_MIN[7:0]
register further scales the minimum bus idle time by a factor of 4.

Fixes: aa874cdfec07 ("i2c: mchp-pci1xxxx: Update Timing registers")
Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
---
 drivers/i2c/busses/i2c-mchp-pci1xxxx.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mchp-pci1xxxx.c b/drivers/i2c/busses/i2c-mchp-pci1xxxx.c
index 5ef136c3ecb1..cb9455b38c1d 100644
--- a/drivers/i2c/busses/i2c-mchp-pci1xxxx.c
+++ b/drivers/i2c/busses/i2c-mchp-pci1xxxx.c
@@ -190,9 +190,9 @@
  * Bus Idle Minimum time = BUS_IDLE_MIN[7:0] x Baud_Clock_Period x
  * (BUS_IDLE_MIN_XK_TICKS[7] ? 4,1)
  */
-#define BUS_IDLE_MIN_100K_TICKS		36UL
-#define BUS_IDLE_MIN_400K_TICKS		10UL
-#define BUS_IDLE_MIN_1000K_TICKS	4UL
+#define BUS_IDLE_MIN_100K_TICKS		165
+#define BUS_IDLE_MIN_400K_TICKS		40
+#define BUS_IDLE_MIN_1000K_TICKS	16
 
 /*
  * CTRL_CUM_TIME_OUT_XK_TICKS defines SMBus Controller Cumulative Time-Out.
-- 
2.25.1