Re: [PATCH 1/2] i2c: tegra: Add logic to support different register offsets

Jon Hunter
2025-10-24T15:33:49Z

On 01/10/2025 16:36, Kartik Rajput wrote:
> Tegra410 use different offsets for existing I2C registers, update
> the logic to use appropriate offsets per SoC.
>
> Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
> ---
> drivers/i2c/busses/i2c-tegra.c | 499 ++++++++++++++++++++++-----------
> 1 file changed, 334 insertions(+), 165 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index 038809264526..1e26d67cbd30 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c

...

> +static const struct tegra_i2c_regs tegra20_i2c_regs_dvc = {
> + .cnfg = 0x000 + 0x40,
> + .status = 0x01c + 0x40,
> + .sl_cnfg = 0x020 + 0x40,
> + .sl_addr1 = 0x02c + 0x40,
> + .sl_addr2 = 0x030 + 0x40,
> + .tlow_sext = 0x034 + 0x40,
> + .tx_fifo = 0x050 + 0x10,
> + .rx_fifo = 0x054 + 0x10,
> + .packet_transfer_status = 0x058 + 0x10,
> + .fifo_control = 0x05c + 0x10,
> + .fifo_status = 0x060 + 0x10,
> + .int_mask = 0x064 + 0x10,
> + .int_status = 0x068 + 0x10,
> + .clk_divisor = 0x06c + 0x10,
> + .bus_clear_cnfg = 0x084 + 0x40,
> + .bus_clear_status = 0x088 + 0x40,
> + .config_load = 0x08c + 0x40,
> + .clken_override = 0x090 + 0x40,
> + .interface_timing_0 = 0x094 + 0x40,
> + .interface_timing_1 = 0x098 + 0x40,
> + .hs_interface_timing_0 = 0x09c + 0x40,
> + .hs_interface_timing_1 = 0x0a0 + 0x40,
> + .master_reset_cntrl = 0x0a8 + 0x40,
> + .mst_fifo_control = 0x0b4 + 0x10,
> + .mst_fifo_status = 0x0b8 + 0x10,
> + .sw_mutex = 0x0ec + 0x40,

sw_mutex is not supported for Tegra20 or anything before Tegra264.

Jon

--
nvpublic