[PATCH] i2c: allow ddr5 ram page change with active intel spd write protection

["Blacktempel (Florian K.)" <florian.blacktempel@gmail.com>]

SPD of most Intel DDR5 systems is write protected.
The write protection also includes changing page, via MR11 register, and prevents reading data.

This patch allows page changing with write protection active via a I2C_SMBUS_READ on PROC_CALL.
That is a, publicly undocumented, Intel specific way to allow page change.

Link: https://github.com/Blacktempel/RAMSPDToolkit/issues/4
Link: https://github.com/Blacktempel/RAMSPDToolkit/blob/9b2aeab9b7637be1874520c74c9873e174fe4947/RAMSPDToolkit/SPD/DDR5AccessorBase.cs#L237
Link: https://github.com/namazso/PawnIO.Modules/pull/19/files#diff-43cf449eaf4b834c447bc85ad039882fbd4fc883be00447908b94eb9cc8a9c36R481
Signed-off-by: Blacktempel (Florian K.) <Blacktempel@hotmail.de>
---
 drivers/i2c/busses/i2c-i801.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index cba992fa6557..9d8eda8b3287 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -788,7 +788,7 @@ static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data
 		xact = I801_WORD_DATA;
 		break;
 	case I2C_SMBUS_PROC_CALL:
-		i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
+		i801_set_hstadd(priv, addr, read_write);
 		iowrite8(data->word & 0xff, SMBHSTDAT0(priv));
 		iowrite8((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 		iowrite8(hstcmd, SMBHSTCMD(priv));

base-commit: 0739473694c4878513031006829f1030ec850bc2
--