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Wed, 5 Nov 2025 22:17:34 -0800 From: Akhil R To: CC: , , , , , , , , , , , , Subject: Re: [PATCH v9 2/4] i2c: tegra: Add HS mode support Date: Thu, 6 Nov 2025 11:47:33 +0530 Message-ID: <20251106061733.36157-1-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <84f7f5d4-bb6a-4e2a-9579-0d957b692de2@nvidia.com> References: <84f7f5d4-bb6a-4e2a-9579-0d957b692de2@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD80:EE_|MN0PR12MB6080:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c776e92-2e76-4651-d442-08de1cfc39dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|30052699003|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?69K0YSRkbESDQEQjF5UEFXWmbTCuQjeZOSc0xYuh1FpUjeM6VEmIguPp3Fft?= =?us-ascii?Q?PRKF3NgLxYz+ZVIwhcgGMgud1U0MpKgJ45E2U9loCzYsadK3Jx7I+L0DBjZm?= =?us-ascii?Q?DSzIZbo1pd5AraEqTxZDEa+ZO4lTyrMIywOP6077a2iXJd1JTCY7j9b1+Lil?= =?us-ascii?Q?QShhFIWPOX6FkEILs086DWFkrdgH8BZkd9h7pJizMWCFZ7zxORcQuyQHEPjl?= =?us-ascii?Q?d7D9gEWBA0bZ9XRQNQys+agJtS6YvxJwcP2xmp9o5g5kG7+8POc/a12Db4CQ?= =?us-ascii?Q?g25ETFaubKDeRAG43ybKJWjhkpOOD0aJ56mwJ/Tly10Ph77T7xTT339Wcby2?= =?us-ascii?Q?WJLW5fU976YCkwGX4WkbETsrbpfNHSBk05MegN6GGEGT0388oIvhlyDxCIz6?= =?us-ascii?Q?MAy6axwvJjqbs60gWXVL8nSN+g8e8hBSdh6bgf4AbD25bfZfl8IZn1WnbGdv?= =?us-ascii?Q?dmgLOZfyAWAThwKNvUhF+GXfcdqJ2TtKR3pC7H6/L6QGqr8+iM3Blm6tkL8s?= =?us-ascii?Q?wsgDsEhaqSto9KOuR1a4FSMxjB6YOlkXgeD+HG6CNgj4b/nXY9+pyeaQ+3Wr?= =?us-ascii?Q?Hh80+6QBO5ocKFpxH/L+ArSqy9ueDMZVeCE7PFB5mEkQeKDvrBuAgjjOL8Xj?= =?us-ascii?Q?6MPsCuDkNdIN7x+Xob4LlQIwm2GNXI2st0TMTCKVV8lfvWcKNPEPvZ1xPBDb?= =?us-ascii?Q?MbS7VZ0n9yd/X5lIXsLiglun/9NF1QwBYIgfPiYNKN+mgHmP11kmujzpFV+n?= =?us-ascii?Q?sj2S/LAOZAVvLGyu3ZlTEHRLkwSFjgQRVUbk4+NBqyfErHW4R0kQs57O5GcH?= =?us-ascii?Q?b8S7+kM8JABgkOjDjPFWyaqOXDFZo1pvoD3xzmn8ZcU+XMqW6HpkoA0g4M/h?= =?us-ascii?Q?qFhrnkpOfsGzkqKczAy+1yJCHjodU11ZcAYsESmf+voYvMCgpTxNjwTRGN+l?= =?us-ascii?Q?EjSqFPBGjWVDGjVYYBA4oki/A9COGd3ek6JR8a35fk9ohTUWWVKbDu+nw47q?= =?us-ascii?Q?PYSaKptRN//mUVSIS8e5SBMgElmgQq+aN7J00Tq9EPnk9ZflzrS67swKovHU?= =?us-ascii?Q?b2nwovSGvaqmXTyjIj+1O7CefvEgGERjJZ7FQUT6BZsPljGAjeGY1V0dyfVS?= =?us-ascii?Q?6aF5UKjHygZ9sPHcixJt7T9JPMnMT9kF3reNCM09cWF1bkg4b1rrMqxJrWhT?= =?us-ascii?Q?JvDGgBq4u/SGLZSIqAy5YqHSysTNEzNqE2c0AFOdhNS4xG2YXb8d0j29h0j7?= =?us-ascii?Q?YoGWXy2NH+ejb9j8+Bpc1sNDT9Q1oHmtcdVXtxo8J6oY7CWFm5KhvzvQBIY/?= =?us-ascii?Q?rmrfnqYn7TqlDaNIZfdZ3bPn/MkIpyiCfOT4iQ/tyMfCgGPZx+HgcRk3TLZk?= =?us-ascii?Q?xfioHt9j/QsxDRnRsySnPRL0QSrGPh1oH3/7f292WPmhrK4oziGSuyDbN4Yk?= =?us-ascii?Q?vZgZ8KiSyXsPNnTK4OJwHJyRyZCkMmrD4K69BDejXjcl1YJu4NOQJT0+vnix?= =?us-ascii?Q?EyxY0ITZS4eeCVLWot8qY+wxNkMS7dDRC7hKAMVxtPmPCOAkZe3w2ZVeyUQe?= =?us-ascii?Q?3MlS6zTRfBgaOeIHtn0=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(30052699003)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2025 06:17:55.9395 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c776e92-2e76-4651-d442-08de1cfc39dc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD80.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6080 On Fri, 24 Oct 2025 16:28:50 +0100, Jon Hunter wrote: > On 01/10/2025 07:47, Kartik Rajput wrote: ... >> /** >> @@ -678,16 +685,28 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) >> tegra_i2c_vi_init(i2c_dev); >> >> switch (t->bus_freq_hz) { >> - case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: >> default: >> + if (!i2c_dev->hw->has_hs_mode_support) >> + t->bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ; >> + fallthrough; >> + >> > This looks odd. I guess this is carry over from the previous code, but > now it looks very odd to someone reviewing the code after this change > has been made. We need to make the code here more logical so that the > reader stands a chance of understanding the new logic. Would it look better if I update as below? @@ -678,8 +685,26 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) tegra_i2c_vi_init(i2c_dev); switch (t->bus_freq_hz) { - case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: default: + /* + * When HS mode is supported, the non-hs timing registers will be used for the + * master code byte for transition to HS mode. As per the spec, the 8 bit master + * code should be sent at max 400kHz. Therefore, limit the bus speed to fast mode. + * Whereas when HS mode is not supported, allow the highest speed mode capable. + */ + if (i2c_dev->hw->has_hs_mode_support) { + tlow = i2c_dev->hw->tlow_fast_fastplus_mode; + thigh = i2c_dev->hw->thigh_fast_fastplus_mode; + tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; + non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; + + break; + } else { + t->bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ; + } + fallthrough; + + case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: tlow = i2c_dev->hw->tlow_fast_fastplus_mode; thigh = i2c_dev->hw->thigh_fast_fastplus_mode; tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; @@ -688,6 +713,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) ... >> @@ -717,6 +736,18 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) >> if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) >> i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); >> >> >> + /* Write HS mode registers. These will get used only for HS mode*/ >> + if (i2c_dev->hw->has_hs_mode_support) { >> + tlow = i2c_dev->hw->tlow_hs_mode; >> + thigh = i2c_dev->hw->thigh_hs_mode; >> + tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode; >> + >> + val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) | >> + FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow); >> + i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0); >> + i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1); >> + } >> + > > I still think all of the above needs a bit of work. I suppose the above section can be as is since HS mode registers are independent of other speed modes. Any suggestions or thoughts? Regards, Akhil