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Mon, 10 Nov 2025 00:05:21 -0800 From: Kartik Rajput To: , , , , , , , , , , , , , CC: Subject: [PATCH v10 3/4] i2c: tegra: Add support for SW mutex register Date: Mon, 10 Nov 2025 13:35:01 +0530 Message-ID: <20251110080502.865953-4-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251110080502.865953-1-kkartik@nvidia.com> References: <20251110080502.865953-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D6:EE_|IA1PR12MB7518:EE_ X-MS-Office365-Filtering-Correlation-Id: d836173b-0bf1-4eab-651b-08de202fefc2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?tCDaiz5O8SM1nhcEjwMaxjNl8g2IV0wSCyMq4KpfF3rOzA2teMj2hfABNQsc?= =?us-ascii?Q?73Bst++uOrV3a+NNkRe8iEfLcpjee7XflzxzDHx42VJWsjnWV5QUENAjMxK4?= =?us-ascii?Q?M5dLRt03Z8uYUk94QbRNumQDA1bHtyU/Upm3A/cCV7grdZiUM6+TMghj+NAW?= =?us-ascii?Q?YCrvBjKwgkczekf/ukjvkhBXDlKGAfjq16iD5o/RKnUPWy3AOvHuDX+kiM5Q?= =?us-ascii?Q?IsyLAZ49e6mI3OkGKiWPoTtlplgujuhufne+sXVm6I40rMM/MM7qzygVJER5?= =?us-ascii?Q?GvTada8P7nBU7MnB689p9giSMh+8t5YD/Z2NKzHKl4WvP9aoQ3/V/hR2z2dT?= =?us-ascii?Q?NiF7erhZ2wAQNa/R1bvRtP1koOV/gaExH3lY+efCXvpLWvDg1QEw/pAaVIAx?= =?us-ascii?Q?tyA+fReBwqbGVSJMOcrHsYEZIgT0STWeexKn56XU78lHogRsZ7ZdbIRNtUNH?= =?us-ascii?Q?AB5sZz/T+Ahm1fFO/VEw4ZW8vy9FHo+YfcZ4jA5MwzCP1LtExxaauGcKgmYs?= =?us-ascii?Q?ndVOpKug1IImHzSDzHH6GKtOyokk+17xp7Jwi0XE1rTONTtxcczEzjNlFz9F?= =?us-ascii?Q?SIhoQ4qA5PmmovYRtKEdiZQspa6ova/Q+Pl0L7IIxXKY8dRujvRnEPQZyXzc?= =?us-ascii?Q?lHGbbrUJ1psDFf8iTN0RXHlt6TSSPej6e7CRYwfQVzFQW3Osq/9MJh1YpaW0?= =?us-ascii?Q?OsRetKkQ+1+6NrC1R5B0FbSf+zbK7AiTPJeUr5FL0cb0jdJ0g5/98s2znVuu?= =?us-ascii?Q?HT0goUUakSjcw4asCGPcvh9i6rKTHWZY7EOUYrQjp4dtkCDrDbRs9VtJtYTr?= =?us-ascii?Q?lKVucf9OXTbsEC4ogLByqxUOzbT1HmOgVOV7y5woKCEhROCj6vN7VJay+KEg?= =?us-ascii?Q?a5zL6rydehdKyV3Ks2b08Bj1uQ0xRu1c2XZNXAVXhHunhkCj+3EkYG8Ti9gc?= =?us-ascii?Q?u5rMgHjj6YW9mhFUvn/xQJLEGUmv/KzpbWMsXFqX8hSniVaNaGINLbN+yz7W?= =?us-ascii?Q?LYU8Pfq1p+aO87d0JC/z40Pri0H7KYA+nZzbgKW6jNGECSiR7EZxaOIivI1a?= =?us-ascii?Q?j15xrzDkp0MYp4/onCeYqiAySLOM7S2CAJtssAuqqVj6uUmvQcbQz/Bea/J/?= =?us-ascii?Q?zaQylq0wxMxV7fQ3X5ARnaJBfzXigOPrb4JJIz1O20DCR0WouAd1TCUaPZdJ?= =?us-ascii?Q?RLjnvmLQ9mkSHyuXTIVVNMammTrA2xH2ypkDrJiX66aWATDcL1v4cg5ZPojB?= =?us-ascii?Q?xdy0adZX6TpkKrTF+BjAav1N5H2ZFydYayCUk8G3f1VwbNZ4Iap4ZUaikcGT?= =?us-ascii?Q?NEB4mwHF4/qKm1u8yZmywGmUeYmfxm0k2tFYafFty/FRPGJ6AST2g1VBtU+5?= =?us-ascii?Q?DSurBPbH2S/eKw9SMjpuPDMCJj1p52W5l8T+UmFlcvgb/bQHDg9uI8l9sezO?= =?us-ascii?Q?w6K5zAlscqoKzlwuhLzqbMeuA2ZlAt2eHjM9lQ2Cr3Hn7qYCA8tAM2/FyMlG?= =?us-ascii?Q?mnCLTEiT8nJ4FTxDrZFa0qlqUkMG83wI/tc8OjGP6lxfyIlWQncnZvYeY6Re?= =?us-ascii?Q?oj7tHFd52URLRCNZdfYo2RRMVEq5kabGOlPB8Lcn?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2025 08:05:39.0971 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d836173b-0bf1-4eab-651b-08de202fefc2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7518 Add support for SW mutex register introduced in Tegra264 to provide an option to share the interface between multiple firmwares and/or VMs. This involves following steps: - A firmware/OS writes its unique ID to the mutex REQUEST field. - Ownership is established when reading the GRANT field returns the same ID. - If GRANT shows a different non-zero ID, the firmware/OS retries until timeout. - After completing access, it releases the mutex by writing 0. However, the hardware does not ensure any protection based on the values. The driver/firmware should honor the peer who already holds the mutex. Signed-off-by: Kartik Rajput Signed-off-by: Akhil R Reviewed-by: Jon Hunter --- v7 -> v8: * Use `bool` instead of `int` for `locked` variable in tegra_i2c_mutex_lock() function. v6 -> v7: * Return bool from tegra_i2c_mutex_acquired() and tegra_i2c_mutex_trylock() functions. * Move `has_mutex` check inside tegra_i2c_mutex_lock/unlock functions. * Remove redundant empty line added in tegra_i2c_xfer() in v6. * Fix pm_runtime_put() not getting called if mutex unlock fails. * In tegra_i2c_mutex_lock() simplify the logic to check if the mutex is acquired or not by checking the value of `ret` variable. * Update commit message to describe the functioning of SW mutex feature. v4 -> v6: * Guard tegra_i2c_mutex_lock() and tegra_i2c_mutex_unlock() to ensure that they are called on platforms which support SW mutex. v3 -> v4: * Update timeout logic of tegra_i2c_mutex_lock() to use read_poll_timeout APIs for improving timeout logic. * Add tegra_i2c_mutex_acquired() to check if mutex is acquired or not. * Rename I2C_SW_MUTEX_ID as I2C_SW_MUTEX_ID_CCPLEX. * Function tegra_i2c_poll_register() was moved unnecessarily, it has now been moved to its original location. * Use tegra_i2c_mutex_lock/unlock APIs in the tegra_i2c_xfer() function. This ensures proper propagation of error in case mutex lock fails. Please note that as the function tegra_i2c_xfer() is already guarded by the bus lock operation there is no need of additional lock for the tegra_i2c_mutex_lock/unlock APIs. v2 -> v3: * Update tegra_i2c_mutex_trylock and tegra_i2c_mutex_unlock to use readl and writel APIs instead of i2c_readl and i2c_writel which use relaxed APIs. * Use dev_warn instead of WARN_ON if mutex lock/unlock fails. v1 -> v2: * Fixed typos. * Fix tegra_i2c_mutex_lock() logic. * Add a timeout in tegra_i2c_mutex_lock() instead of polling for mutex indefinitely. --- drivers/i2c/busses/i2c-tegra.c | 92 ++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 2038ab2d8095..3513bd5c7c5b 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -137,6 +137,14 @@ #define I2C_MASTER_RESET_CNTRL 0x0a8 +#define I2C_SW_MUTEX 0x0ec +#define I2C_SW_MUTEX_REQUEST GENMASK(3, 0) +#define I2C_SW_MUTEX_GRANT GENMASK(7, 4) +#define I2C_SW_MUTEX_ID_CCPLEX 9 + +/* SW mutex acquire timeout value in microseconds. */ +#define I2C_SW_MUTEX_TIMEOUT_US (25 * USEC_PER_MSEC) + /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 @@ -210,6 +218,7 @@ enum msg_end_type { * @has_interface_timing_reg: Has interface timing register to program the tuned * timing settings. * @has_hs_mode_support: Has support for high speed (HS) mode transfers. + * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -237,6 +246,7 @@ struct tegra_i2c_hw_feature { u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; bool has_hs_mode_support; + bool has_mutex; }; /** @@ -381,6 +391,76 @@ static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); } +static bool tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + val = readl(i2c_dev->base + reg); + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); + + return id == I2C_SW_MUTEX_ID_CCPLEX; +} + +static bool tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + val = readl(i2c_dev->base + reg); + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); + if (id != 0 && id != I2C_SW_MUTEX_ID_CCPLEX) + return false; + + val = FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID_CCPLEX); + writel(val, i2c_dev->base + reg); + + return tegra_i2c_mutex_acquired(i2c_dev); +} + +static int tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev) +{ + bool locked; + int ret; + + if (!i2c_dev->hw->has_mutex) + return 0; + + if (i2c_dev->atomic_mode) + ret = read_poll_timeout_atomic(tegra_i2c_mutex_trylock, locked, locked, + USEC_PER_MSEC, I2C_SW_MUTEX_TIMEOUT_US, + false, i2c_dev); + else + ret = read_poll_timeout(tegra_i2c_mutex_trylock, locked, locked, USEC_PER_MSEC, + I2C_SW_MUTEX_TIMEOUT_US, false, i2c_dev); + + if (ret) + dev_warn(i2c_dev->dev, "failed to acquire mutex\n"); + + return ret; +} + +static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + if (!i2c_dev->hw->has_mutex) + return 0; + + val = readl(i2c_dev->base + reg); + + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); + if (id && id != I2C_SW_MUTEX_ID_CCPLEX) { + dev_warn(i2c_dev->dev, "unable to unlock mutex, mutex is owned by: %u\n", id); + return -EPERM; + } + + writel(0, i2c_dev->base + reg); + + return 0; +} + static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) { u32 int_mask; @@ -1426,6 +1506,10 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], return ret; } + ret = tegra_i2c_mutex_lock(i2c_dev); + if (ret) + return ret; + for (i = 0; i < num; i++) { enum msg_end_type end_type = MSG_END_STOP; @@ -1455,6 +1539,7 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], break; } + ret = tegra_i2c_mutex_unlock(i2c_dev); pm_runtime_put(i2c_dev->dev); return ret ?: i; @@ -1531,6 +1616,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = false, .has_hs_mode_support = false, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { @@ -1557,6 +1643,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = false, .has_hs_mode_support = false, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { @@ -1583,6 +1670,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = false, .has_hs_mode_support = false, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { @@ -1609,6 +1697,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = true, .has_hs_mode_support = false, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { @@ -1635,6 +1724,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .setup_hold_time_hs_mode = 0, .has_interface_timing_reg = true, .has_hs_mode_support = false, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { @@ -1661,6 +1751,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .setup_hold_time_hs_mode = 0, .has_interface_timing_reg = true, .has_hs_mode_support = false, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { @@ -1689,6 +1780,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .setup_hold_time_hs_mode = 0x090909, .has_interface_timing_reg = true, .has_hs_mode_support = true, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra256_i2c_hw = { -- 2.43.0