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Tue, 18 Nov 2025 03:09:04 -0800 From: Akhil R To: CC: , , , , , , , , , , , Subject: Re: [PATCH v12 4/6] i2c: tegra: Add HS mode support Date: Tue, 18 Nov 2025 16:39:02 +0530 Message-ID: <20251118110903.61560-1-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <828b6131-24bf-4a92-9c86-4c9f0461e6d0@nvidia.com> References: <828b6131-24bf-4a92-9c86-4c9f0461e6d0@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F69:EE_|MW3PR12MB4474:EE_ X-MS-Office365-Filtering-Correlation-Id: 9615e57b-e3e4-483c-c021-08de2692ee0c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?axiYw5yWSMbaC7aoNwqOuDEjoASU3evaEdgqaXDT3/OSYpcCKDI8XolVKHHv?= =?us-ascii?Q?l9r/DslT8sp+Olr31oARHMeYR2eGWzTtfPjm/Oare9u9YmVvnzdIA0Lu+iIJ?= =?us-ascii?Q?s80YjPjVKcgiaAF0x4QRZn1bgjNi2ZOB0OBhg+pn1gxzRmB8+c2EgdtmbK+F?= =?us-ascii?Q?p/WLwwCX0ZMaP9iKFUAxdK1+chHzI604PDWfTKbKVgU8nSAZToxs2721GhC3?= =?us-ascii?Q?WzmtX1WHQyScrtiOg3SJLE3WfXCjrh0EfpPLPCNS6ZhR5v3ntcNyKvYOOjXd?= =?us-ascii?Q?2njhWM5iwfNkicZS61T6WKR8qZzd1nbtXl9w7j01rwblFUT/3xqrSKL48Nv9?= =?us-ascii?Q?pg052GPceb2ByXb0CALnRqPN+zC8K92yVBaHq6dakATrYDZdvNZgFtj5k5Un?= =?us-ascii?Q?nD8B2uNriGniC+ZifLABiaIU/pxm6BurtkZr4kTnfyQ40tRqMNHfA2CJrtVh?= =?us-ascii?Q?SISoss7FQYT6Xq03qGPIwLH5w8/A9kCyU16fTZ8oo3baWcj5gYE1+d2QGzIB?= =?us-ascii?Q?p1XoHr6i8gMwOkC3Ss8FoGvTtz+5lEG75ndHLtb7O+OpWrPbLglfiHROV53/?= =?us-ascii?Q?IEwm8YhPXfTI3WQzqBI7LmU+3A4v/kmVtdYSRHW0SLNllJBQlIvBz3lDcn6c?= =?us-ascii?Q?Y8/81l6+i4d+DzhqySDjpwwCTIvDv/aOoZe0MFRnLsZuckGLc7H0SRzyORke?= =?us-ascii?Q?ltMw5Zvhb083MylXiYJ5JqB2DjtKR3cB3QFJy/gv0HjfrEqhuDMHuEl2CZop?= =?us-ascii?Q?Jv9/El6HTRxJluXGlZdn12soIxrW8rNsc9hN5fjimcO1DYKECFQ9a3CgCzVl?= =?us-ascii?Q?jf7iYejpjJoD0D+tpU3O3gdMLHK555bA3VJTEvyyGoX4nknNyFeDTz/6saYV?= =?us-ascii?Q?ZPLMbBDFP/n6dwiNGtCstWlPTUSBHRaad8lu/N5kxmYsq57Bzeu75MvvfgRM?= =?us-ascii?Q?rVJQsb6pe5KmB+h8Vs/u3LqTbUKrbg4eea/xsOGKkzhobj+ZspfuGUfvVZCJ?= =?us-ascii?Q?9pJJ0yd0H0EzVCI8YMiRAUuz/dC8lsCbPvLHpkGgQ80lYo4qEax2jaKHEDAT?= =?us-ascii?Q?Hslts7rcR8KCOMPs+7+iozTMVBVjdKajXR9xA7xk5hhxZ9ASAPS4jE2Xo5+r?= =?us-ascii?Q?6yqXac7mIp7habvCa3nKq8Mvckie8c4rdNRkBvX5vSZJmYYXJbEmvfYAdCOQ?= =?us-ascii?Q?ub01W+8THUecW9/cqQULmt7TAwqF8ytQkhpcBegMOWAy7cQhi4SXgY4tJGIt?= =?us-ascii?Q?cRJB/lVmgC3yVWkEgZsHtVNpGupz3pTfmQ6yic1bt5d9kCBjXr2xnD1B+pO9?= =?us-ascii?Q?yrZJVWd8xMhyKBQKSCyjLowgl3iFmHsuOo4Wf/xPtP4//6+ww/Ffr+eYkHiM?= =?us-ascii?Q?gVhVcMCzgtu6kjDi56NKKLksQ/gBBo2Tq622Q3LNYaYl4W87HkxXWCLOMLSa?= =?us-ascii?Q?kILAB6dO4S0ou+xdXllpmUJYzBlgX/fckawzVWLo0nBPJi1i00P4GknxOG12?= =?us-ascii?Q?puUaXJ+wa483/etNvDXK+9y+TYw5lrD685WPzSWalI9NYgyyIVkCwy+ed28I?= =?us-ascii?Q?svlJlGcGM+yW6xr43Ptm2YYvDTXHI+KPKh6PuM3q?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2025 11:09:23.2774 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9615e57b-e3e4-483c-c021-08de2692ee0c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F69.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4474 On Mon, 17 Nov 2025 11:07:07 +0000, Jon Hunter wrote: > On 15/11/2025 04:26, Akhil R wrote: >> Add support for HS (High Speed) mode transfers, which is supported by >> Tegra194 onwards. Also adjust the bus frequency such that it uses the >> fast plus mode when HS mode is not supported. >> >> Signed-off-by: Akhil R >> Signed-off-by: Kartik Rajput >> --- >> v10 -> v12: >> * Update bus_freq_hz to max supported freq and updates to >> accomodate the changes from Patch 2/6. >> v10 -> v11: >> * Update the if condition as per the comments received on: >> https://lore.kernel.org/linux-tegra/20251110080502.865953-1-kkartik@nvidia.com/T/#t >> v9 -> v10: >> * Change switch block to an if-else block. >> v5 -> v9: >> * In the switch block, handle the case when hs mode is not >> supported. Also update it to use Fast mode for master code >> byte as per the I2C spec for HS mode. >> v3 -> v5: >> * Set has_hs_mode_support to false for unsupported SoCs. >> v2 -> v3: >> * Document tlow_hs_mode and thigh_hs_mode. >> v1 -> v2: >> * Document has_hs_mode_support. >> * Add a check to set the frequency to fastmode+ if the device >> does not support HS mode but the requested frequency is more >> than fastmode+. >> --- >> drivers/i2c/busses/i2c-tegra.c | 59 ++++++++++++++++++++++++++++++++-- >> 1 file changed, 57 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c >> index 8a696c88882e..9ebeb6a2eaf5 100644 >> --- a/drivers/i2c/busses/i2c-tegra.c >> +++ b/drivers/i2c/busses/i2c-tegra.c >> @@ -91,6 +91,7 @@ >> #define I2C_HEADER_IE_ENABLE BIT(17) >> #define I2C_HEADER_REPEAT_START BIT(16) >> #define I2C_HEADER_CONTINUE_XFER BIT(15) >> +#define I2C_HEADER_HS_MODE BIT(22) > > This should be ordered according to the value. So place this above > I2C_HEADER_CONT_ON_NAK. Agree. Do we need a new version with this change or would it be possible to update while applying? Regards, Akhil