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Tue, 5 May 2026 03:59:48 -0700 From: Akhil R To: Laxman Dewangan , Dmitry Osipenko , Andi Shyti , Thierry Reding , Jonathan Hunter , "Kartik Rajput" , Wolfram Sang , , , CC: , Akhil R Subject: [PATCH 1/4] i2c: tegra: use dmaengine_get_dma_device() for DMA buffer allocation Date: Tue, 5 May 2026 16:29:25 +0530 Message-ID: <20260505105928.38457-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260505105928.38457-1-akhilrajeev@nvidia.com> References: <20260505105928.38457-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6C:EE_|CH1PR12MB9599:EE_ X-MS-Office365-Filtering-Correlation-Id: d65fc1e0-e36a-452a-4e3e-08deaa9575fb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|921020|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: juVmsdPOlRCaYQ1o2JL7ANkmkjKWhCk3/45R2FVkc1wTJRmaqXOcDLUqxBfent6iWLC7UaaYf9Cgv+R1nwV9Pzq32X4myw4LjfZs8/Cg+Jxb9BmPiVQvIzpyFezhfyZcXb6yNKwDfqfjcGBHGRPa4Ens1cGBsUz3Q2qWyDgasL3ReuBR4AzhQs/V9lWWmpPT/pN3k/xM8awT5ykA5m+OYjdkUrLT66X8qfAR0MHTbK3V6kQmm4Cz+amxloyxG+h9rPI0M6aCQWFi1DSSF6SWSuasryKGwVACz1rAVkGMsKGUX8XBQgaAllLPIQzdijQmg5xQ2dlM2984NF5irfUyI9Du5aREDij8POX44Dphe4rcB8aHj9U4wvyA1bewPG866pZJf6ayGeeUtIX/OGfkeUv+LN/5sHyaYmEeU9ui9LXNISPh68IdrBSQJktA29qX X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2026 11:00:03.7572 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d65fc1e0-e36a-452a-4e3e-08deaa9575fb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9599 Use dmaengine_get_dma_device() to obtain the correct struct device pointer for dma_alloc_coherent() instead of directly dereferencing chan->device->dev. The dmaengine_get_dma_device() helper checks whether the DMA channel has a per-channel DMA device (chan->dev->chan_dma_dev) and returns it when available, falling back to the controller device otherwise. On platforms where the DMA controller sits behind an IOMMU with per-channel IOVA spaces (e.g. Tegra264 GPC DMA), the per-channel device carries the correct DMA mapping context. Using the controller device directly would allocate DMA buffers against the wrong IOMMU domain, leading to SMMU faults at runtime. On platforms without per-channel DMA devices the helper returns the same pointer as before, so there is no change in behavior for existing hardware. Signed-off-by: Akhil R Assisted-by: Cursor:claude-4.6-opus --- drivers/i2c/busses/i2c-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 9fd5ade774a0..a21f6457d41b 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -712,7 +712,7 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) goto err_out; } - i2c_dev->dma_dev = i2c_dev->dma_chan->device->dev; + i2c_dev->dma_dev = dmaengine_get_dma_device(i2c_dev->dma_chan); i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + I2C_PACKET_HEADER_SIZE; -- 2.50.1