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Mon, 18 May 2026 04:40:29 -0700 From: Akhil R To: Laxman Dewangan , Dmitry Osipenko , Andi Shyti , Thierry Reding , Jonathan Hunter , "Kartik Rajput" , Wolfram Sang , , , CC: Akhil R Subject: [PATCH v2 2/4] i2c: tegra: Disable fair arbitration for non-MCTP buses Date: Mon, 18 May 2026 17:10:11 +0530 Message-ID: <20260518114013.62065-3-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260518114013.62065-1-akhilrajeev@nvidia.com> References: <20260518114013.62065-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D9:EE_|DS5PPFE52C859EE:EE_ X-MS-Office365-Filtering-Correlation-Id: 757fdfb0-57d0-4e5f-4857-08deb4d24c61 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|22082099003|3023799003|56012099003|921020|18002099003|11063799003; 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It is enabled by default, adding a per-transfer latency overhead that impacts non-MCTP I2C buses. Disable the fairness arbitration register during controller init for buses that are not MCTP controllers. Assisted-by: Cursor:claude-4.6-opus Reviewed-by: Jon Hunter Signed-off-by: Akhil R --- drivers/i2c/busses/i2c-tegra.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index a21f6457d41b..f96a118249b3 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -164,6 +164,7 @@ struct tegra_i2c_regs { unsigned int master_reset_cntrl; unsigned int mst_fifo_control; unsigned int mst_fifo_status; + unsigned int fairness_arb; unsigned int sw_mutex; }; @@ -272,6 +273,7 @@ static const struct tegra_i2c_regs tegra264_i2c_regs = { .master_reset_cntrl = 0x0a8, .mst_fifo_control = 0x0b4, .mst_fifo_status = 0x0b8, + .fairness_arb = 0x0e8, .sw_mutex = 0x0ec, }; @@ -300,6 +302,7 @@ static const struct tegra_i2c_regs tegra410_i2c_regs = { .master_reset_cntrl = 0x0ac, .mst_fifo_control = 0x0b8, .mst_fifo_status = 0x0bc, + .fairness_arb = 0x0ec, .sw_mutex = 0x0f0, }; @@ -379,6 +382,7 @@ enum tegra_i2c_variant { * timing settings. * @enable_hs_mode_support: Enable support for high speed (HS) mode transfers. * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs. + * @has_fairarb_reg: Has fairness arbitration register for SMBUS/MCTP support. * @variant: This represents the I2C controller variant. * @regs: Register offsets for the specific SoC variant. */ @@ -412,6 +416,7 @@ struct tegra_i2c_hw_feature { bool has_interface_timing_reg; bool enable_hs_mode_support; bool has_mutex; + bool has_fairarb_reg; enum tegra_i2c_variant variant; const struct tegra_i2c_regs *regs; }; @@ -436,6 +441,7 @@ struct tegra_i2c_hw_feature { * @msg_read: indicates that the transfer is a read access * @timings: i2c timings information like bus frequency * @multimaster_mode: indicates that I2C controller is in multi-master mode + * @is_mctp: indicates that the I2C controller is used as an MCTP controller * @dma_chan: DMA channel * @dma_phys: handle to DMA resources * @dma_buf: pointer to allocated DMA buffer @@ -476,6 +482,7 @@ struct tegra_i2c_dev { void *dma_buf; bool multimaster_mode; + bool is_mctp; bool atomic_mode; bool dma_mode; bool msg_read; @@ -914,6 +921,10 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) if (IS_VI(i2c_dev)) tegra_i2c_vi_init(i2c_dev); + /* Disable fairness arbitration if not an MCTP controller */ + if (i2c_dev->hw->has_fairarb_reg && !i2c_dev->is_mctp) + i2c_writel(i2c_dev, 0, i2c_dev->hw->regs->fairness_arb); + if (i2c_dev->hw->enable_hs_mode_support) max_bus_freq_hz = I2C_MAX_HIGH_SPEED_MODE_FREQ; else @@ -1779,6 +1790,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .has_interface_timing_reg = false, .enable_hs_mode_support = false, .has_mutex = false, + .has_fairarb_reg = false, .variant = TEGRA_I2C_VARIANT_DEFAULT, .regs = &tegra20_i2c_regs, }; @@ -1812,6 +1824,7 @@ static const struct tegra_i2c_hw_feature tegra20_dvc_i2c_hw = { .has_interface_timing_reg = false, .enable_hs_mode_support = false, .has_mutex = false, + .has_fairarb_reg = false, .variant = TEGRA_I2C_VARIANT_DVC, .regs = &tegra20_dvc_i2c_regs, }; @@ -1845,6 +1858,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .has_interface_timing_reg = false, .enable_hs_mode_support = false, .has_mutex = false, + .has_fairarb_reg = false, .variant = TEGRA_I2C_VARIANT_DEFAULT, .regs = &tegra20_i2c_regs, }; @@ -1877,6 +1891,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .has_interface_timing_reg = false, .enable_hs_mode_support = false, .has_mutex = false, + .has_fairarb_reg = false, .variant = TEGRA_I2C_VARIANT_DEFAULT, .regs = &tegra20_i2c_regs, }; @@ -1909,6 +1924,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .has_interface_timing_reg = true, .enable_hs_mode_support = false, .has_mutex = false, + .has_fairarb_reg = false, .variant = TEGRA_I2C_VARIANT_DEFAULT, .regs = &tegra20_i2c_regs, }; @@ -1941,6 +1957,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .has_interface_timing_reg = true, .enable_hs_mode_support = false, .has_mutex = false, + .has_fairarb_reg = false, .variant = TEGRA_I2C_VARIANT_DEFAULT, .regs = &tegra20_i2c_regs, }; @@ -1974,6 +1991,7 @@ static const struct tegra_i2c_hw_feature tegra210_vi_i2c_hw = { .has_interface_timing_reg = true, .enable_hs_mode_support = false, .has_mutex = false, + .has_fairarb_reg = false, .variant = TEGRA_I2C_VARIANT_VI, .regs = &tegra210_vi_i2c_regs, }; @@ -2007,6 +2025,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .has_interface_timing_reg = true, .enable_hs_mode_support = false, .has_mutex = false, + .has_fairarb_reg = false, .variant = TEGRA_I2C_VARIANT_DEFAULT, .regs = &tegra20_i2c_regs, }; @@ -2041,6 +2060,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .has_interface_timing_reg = true, .enable_hs_mode_support = true, .has_mutex = false, + .has_fairarb_reg = false, .variant = TEGRA_I2C_VARIANT_DEFAULT, .regs = &tegra20_i2c_regs, }; @@ -2075,6 +2095,7 @@ static const struct tegra_i2c_hw_feature tegra256_i2c_hw = { .has_interface_timing_reg = true, .enable_hs_mode_support = true, .has_mutex = true, + .has_fairarb_reg = true, .variant = TEGRA_I2C_VARIANT_DEFAULT, .regs = &tegra264_i2c_regs, }; @@ -2109,6 +2130,7 @@ static const struct tegra_i2c_hw_feature tegra264_i2c_hw = { .has_interface_timing_reg = true, .enable_hs_mode_support = true, .has_mutex = true, + .has_fairarb_reg = true, .variant = TEGRA_I2C_VARIANT_DEFAULT, .regs = &tegra264_i2c_regs, }; @@ -2143,6 +2165,7 @@ static const struct tegra_i2c_hw_feature tegra410_i2c_hw = { .has_interface_timing_reg = true, .enable_hs_mode_support = true, .has_mutex = true, + .has_fairarb_reg = true, .variant = TEGRA_I2C_VARIANT_DEFAULT, .regs = &tegra410_i2c_regs, }; @@ -2175,6 +2198,7 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); i2c_dev->multimaster_mode = multi_mode; + i2c_dev->is_mctp = device_property_present(i2c_dev->dev, "mctp-controller"); } static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) -- 2.50.1