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Sat, 01 Aug 2026 13:10:50 -0700 (PDT) X-Received: by 2002:a05:622b:89:10b0:52b:6543:d8a with SMTP id d75a77b69052e-52b654316e8mr27140481cf.26.1785615050027; Sat, 01 Aug 2026 13:10:50 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.na.qualcomm.com ([2a01:e0a:830:450:61cd:dcd3:c61a:ac3c]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1fd4537755sm358499066b.54.2026.08.01.13.10.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Aug 2026 13:10:48 -0700 (PDT) From: Loic Poulain Subject: [PATCH v4 0/5] i2c: qcom-cci: Enforce the required CCI clock rate Date: Sat, 01 Aug 2026 22:10:42 +0200 Message-Id: <20260801-cci-clk-fix-v4-0-e1d80da54e01@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAMJSbmoC/3XMTQ6CMBCG4auYri3pD6XgynsYF6VMpRGottpoC He3sIIEN5O8XzLPiAJ4CwGdDiPyEG2wbkiRHw9It2q4AbZNasQIK4hkFGttse7u2NgPNkBzUTO ljZIofTw8pHnRLtfUrQ0v578LHum87juRYoIFKJClJKRR5dmFkD3fqtOu77N00MxFtibklmCJ0 LwSpWFlTXLxh+BrotoSPBGGa8lpQ0VVwA4xTdMPDuMTFzMBAAA= X-Change-ID: 20260721-cci-clk-fix-fe145b2acfa7 To: Robert Foss , Andi Shyti , Wolfram Sang , Dmitry Baryshkov , Luca Weiss Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, vladimir.zapolskiy@linaro.org, konradybcio@kernel.org, stephan.gerhold@linaro.org, Loic Poulain , Konrad Dybcio , Wenmeng Liu X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAxMDE2MiBTYWx0ZWRfXwhMJxBfHcEaT w/sZmoM/E0TYb/oRfN5BcCFXDf5IZiBS/DIiapAI4byhIWFiJ1pNDIrTCExQaQwEdYpwftSRkVn rXI1i8/jSCirtOBx8fjYmjEXZHvcJskLEeqmNhhtYr38OIOsBSvNeP1OkPhDt7pRJ8ZcxRlWzH6 cd5pgteiIE5qOGTDKFn8tntl4+HoNspE/JnM1IJR56uRNdfk1RG2lXNB1Xpv+qOQtKsrkIcmXFM xQu4iy2sVYGd8YtrRWwn1ZxT8pnZWuyencNDvhuJGLNCEnI57tet353Wqn2DarztPEY1h1m6rw9 lRVOJM5s4vhe0waZN+6P6ocO0RF4SjQd2RwkOPTSiqU+ZTqAJ5YnY1DR/Gyj+oXK7vQxDQLSu6z xeBNzW7klLLZa3H/don6uj+jsUwkuYaiaxRtc3P3H/CIBfxoYbOja5JyiXKaf7hpjD5pvgi89VD BHwbgsc5WybxCeqm9dw== X-Proofpoint-GUID: xEr8fNCu2rh_-0e0njr1SguA8qcCCnTG X-Authority-Analysis: v=2.4 cv=T9C8ifKQ c=1 sm=1 tr=0 ts=6a6e52cb cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=BDIs8drXFFqd0dwbxQcA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODAxMDE2MiBTYWx0ZWRfX7rV/x8kEiNvR SHNbQF25IUj2AgYhRxI7NoEipjRnygiogPupAsoexxKnrfyxhaVokA7I8czf5gUiS07twvNkVDh yAtaSjPsDUP3cP1MVppOyLHstg2yXNk= X-Proofpoint-ORIG-GUID: xEr8fNCu2rh_-0e0njr1SguA8qcCCnTG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-01_03,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608010162 The CCI hw_params timing values (thigh, tlow, etc.) are expressed in clock ticks and are only valid at the specific CCI clock rate they were calibrated for. Running at the wrong rate causes incorrect I2C timings that may violate the I2C specification. Today the rate is left to the DT (assigned-clock-rates) or the bootloader, which is fragile: the driver owns the hw_params and should own the clock rate too. - Move the msm8953 to reusing the common v2 config. - Turn the timing table into a two-dimensional [mode][rate] - Add the 19.2 MHz Standard/Fast timing sets for the v2 CCI - Promote v2 to the generic common table for all revisions - Actively enforce the required rate. This ordering also addresses Vladimir's point that the clock rate is a property of the mode/timing settings rather than of the CCI revision. the per-mode [mode][rate] table lands first, and rate enforcement is built on top of it. Patches 2/5 and 4/5 are the result of discussions with Vladimir and some code sharing. I would expect him to add a Co-developed-by and corresponding Signed-off-by tag if he agrees that the submitted implementation still matches his original intent. Signed-off-by: Loic Poulain --- Changes in v4: - Rebase on andy/i2c/i2-next (527dd7fb6209) (Andy) - Add 'select PM_OPP' to i2c qcom cci Kconfig (Andy) - Link to v3: https://lore.kernel.org/r/20260729-cci-clk-fix-v3-0-f3c731d1596e@oss.qualcomm.com Changes in v3: - Reorder the series so per-mode clock support comes before rate enforcement. Introduce a [rate][mode] timing table and select the row matching the running clock rate. (Vladimir) - The per-mode patch only validates the running rate (error out on a missing entry), the following patches enforce it. - Split the addition of the v2 19.2 MHz Standard/Fast timings into its own patch, keeping the [rate][mode] conversion a pure refactor. - Drop the "Revert ... Remove unused struct member cci_clk_rate" patch: the per-mode [mode][rate] table replaces cci_clk_rate entirely. - Introduce a common params table (revision agnostic) (Vladimir) - Link to v2: https://lore.kernel.org/r/20260727-cci-clk-fix-v2-0-c3958f28b045@oss.qualcomm.com Changes in v2: - Instead of adding a 19.2 MHz cci_clk_rate for msm8953, switch it to the v2 config (37.5 MHz). The msm8953 table was internally inconsistent (Standard/Fast for 19.2 MHz, Fast+ for 37.5 MHz), so a single rate could not satisfy all modes. msm8953 is the same HW version as msm8996/sdm630, which already use v2. (Vladimir) - Remove the msm8953 fix tag (Vladimir) - Apply the rate via the OPP framework instead of a bare clk_set_rate(), managing the vote across runtime PM. (Konrad) - Link to v1: https://lore.kernel.org/r/20260721-cci-clk-fix-v1-0-5eae78700da8@oss.qualcomm.com --- Loic Poulain (5): i2c: qcom-cci: Switch msm8953 to the CCI v2 timing/rate config i2c: qcom-cci: Support per-mode CCI clock rates i2c: qcom-cci: Add 19.2 MHz timings for the v2 CCI i2c: qcom-cci: Share the timing table across CCI revisions i2c: qcom-cci: Enforce the required CCI clock rate drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-qcom-cci.c | 333 ++++++++++++++++++++++---------------- 2 files changed, 196 insertions(+), 138 deletions(-) --- base-commit: 527dd7fb6209857f8ff4426055b3a418e60faa8b change-id: 20260721-cci-clk-fix-fe145b2acfa7 Best regards, -- Loic Poulain