[PATCH] i2c: qcom-cci: enable SCL clock stretching in standard mode on CCI v2

[Hitesh Patel <hitesh@ebytelogic.com>]

The CCI v2 standard-mode (100 kHz) timing table leaves SCL clock
stretching disabled, unlike the fast-plus table for the same block.
A slave that holds SCL low is then not waited for: the master keeps
its own clock timing and the transfer fails with a NACK or returns
corrupt data.

This is hit with a camera reached through a GMSL serializer/
deserializer I2C tunnel (MAX9296A/MAX96717 on the RB3 Gen2 vision
mezzanine). The deserializer acknowledges the address locally, but
forwards the transaction over the coax link and stretches SCL until
the remote side has completed it, which takes well over one clock
period at 100 kHz. Without stretching the register reads of the
sensor behind the link intermittently return garbage and writes are
dropped, which shows up as random sensor init failures.

Clock stretching is part of the I2C specification for every speed
mode and a device that does not stretch is unaffected by enabling it,
so enable it for standard mode as it already is for fast-plus.

Signed-off-by: Hitesh Patel <hitesh@ebytelogic.com>
---
 drivers/i2c/busses/i2c-qcom-cci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c
index 25b6e4e9e..327efa86f 100644
--- a/drivers/i2c/busses/i2c-qcom-cci.c
+++ b/drivers/i2c/busses/i2c-qcom-cci.c
@@ -723,7 +723,7 @@ static const struct cci_data cci_v2_data = {
 		.thd_dat = 22,
 		.thd_sta = 162,
 		.tbuf = 227,
-		.scl_stretch_en = 0,
+		.scl_stretch_en = 1,
 		.trdhld = 6,
 		.tsp = 3
 	},

base-commit: 68142f986ff04b2b70b31db00f719bf690f64a9a
-- 
2.43.0