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Sat, 19 Sep 2026 16:26:53 -0700 (PDT) Received: from cachyos-aura ([45.112.148.107]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c33186490sm7218935eec.18.2026.09.19.16.26.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Sep 2026 16:26:53 -0700 (PDT) From: Navon John Lukose To: Mika Westerberg , Andi Shyti , linux-i2c@vger.kernel.org Cc: Andy Shevchenko , linux-kernel@vger.kernel.org, Navon John Lukose Subject: [PATCH] i2c: designware: size the RX FIFO threshold to the queued transfer Date: Sun, 20 Sep 2026 04:56:47 +0530 Message-ID: <20260919232647.448748-1-navonjohnlukose@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit i2c_dw_xfer_msg() leaves DW_IC_RX_TL at the 0 that i2c_dw_configure_mode() writes, so the controller raises RX_FULL once per received byte. Program RX_TL from the reads already queued, capped at half the FIFO until the last message is queued, so there is room for the rest. On an Arrow Lake-H LPSS core with rx_fifo_depth 32, a 22-byte HID report costs 2.00 interrupts instead of 21.43, and a 452-byte descriptor 0.14 interrupts per byte instead of 1.64. Mean HIDIOCGINPUT latency rises from 2522 to 3268 us; holding /dev/cpu_dma_latency at 0 removes 94% of that. Assisted-by: LLM Signed-off-by: Navon John Lukose --- Tested on my machine, a Lenovo Yoga Pro 7 14IAH10, and one controller, an Intel LPSS core with rx_fifo_depth 32, where it has been the daily driver for the past five days. The half-FIFO cap matches DW_IC_TX_TL. Untested: a RECV_LEN continuation longer than one byte, and cores with rx_fifo_depth below 4. The two interrupts left on a short read are a TX_EMPTY that only runs the state machine and one RX_FULL coalesced with STOP_DET. psys power fell about 1.25 W in one run. It is out of the changelog because the figure depends on how deep the platform idles. drivers/i2c/busses/i2c-designware-master.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c index a1bcc37..f4ad207 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -378,7 +378,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) { struct i2c_msg *msgs = dev->msgs; u32 intr_mask; - int tx_limit, rx_limit; + int tx_limit, rx_limit, rx_tl; u32 buf_len = dev->tx_buf_len; u8 *buf = dev->tx_buf; bool need_restart = false; @@ -484,6 +484,19 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) if (dev->msg_err) intr_mask = 0; + /* + * Size the RX FIFO threshold to the reads already queued, so the + * controller raises one RX_FULL for the whole burst instead of one per + * received byte. While messages remain to be queued, cap it so RX_FULL + * still arrives in time to drain the FIFO and let the next TX_EMPTY + * queue the rest. + */ + rx_tl = dev->rx_outstanding; + if (dev->msg_write_idx < dev->msgs_num) + rx_tl = min_t(int, rx_tl, dev->rx_fifo_depth / 2); + + regmap_write(dev->map, DW_IC_RX_TL, rx_tl ? rx_tl - 1 : 0); + __i2c_dw_write_intr_mask(dev, intr_mask); } -- 2.55.0