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[92.76.89.226]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c3eda5297b0sm96080666b.63.2026.10.15.01.11.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 01:11:36 -0700 (PDT) From: Thilo Zirnstein To: michal.simek@amd.com, andi.shyti@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, Thilo Zirnstein Subject: [PATCH v2 0/1] i2c: i2c-xiic: fix clearing of bnb irq Date: Thu, 15 Oct 2026 10:11:26 +0200 Message-ID: <20261015081127.1566244-1-thi.zirnstein@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Dear all, This patch fixes the clearing routine for the bus not busy (bnb) irq. The bnb is used to indicate that the current transfer is done. A high level view of the software flow for tx: * init i2c controller * prepare all registers ( fill fifo, enable irqs, ... ) * start i2c txfer * clear and enable bnb * wait for completion * ( serve interrupts ) * ( bnb interrupt ): complete completion The datasheet ( pg090-axi-iic, Interrupt-Status-Register ISR) states that the bnb bit can only be cleared if the bus busy bit in the status register is set. So the iic controller must have recognized that their is some activity on the bus. ( Start condition ) Currently the bnb bit is cleared without checking or waiting for this condition. This can lead to spurious bnb interrupts. I am kind of unsure which branch to use for handing in my patch, this one is based i2c/i2c-fixes. Kind regards, Thilo Zirnstein --- Changes in v2: - Unintentional changes removed . Thilo Zirnstein (1): i2c: i2c-xiic: fix clearing of bnb irq drivers/i2c/busses/i2c-xiic.c | 42 +++++++++++++++++++++++++++-------- 1 file changed, 33 insertions(+), 9 deletions(-) -- 2.43.0