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Fri, 16 Oct 2026 01:00:12 -0700 (PDT) X-Received: by 2002:a05:620a:2b42:b0:93c:8e3f:3036 with SMTP id af79cd13be357-93ebd0a1ed0mr3577113085a.4.1792137611802; Fri, 16 Oct 2026 01:00:11 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.na.qualcomm.com ([2a01:e0a:830:450:5402:5e0b:9ef0:9b5b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48dfd4c5942sm5471446f8f.16.2026.10.16.01.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 01:00:10 -0700 (PDT) From: Loic Poulain Subject: [PATCH v3 0/7] i2c: qcom-cci: Runtime capability detection and improved read/write Date: Fri, 16 Oct 2026 10:00:08 +0200 Message-Id: <20261016-cci-imp-v3-0-5ee7ec1ea1a1@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAIjZ0WoC/22Nyw7CIBBFf6VhLQ0MpIIr/8O4oBTtJPYFLdE0/ XdpTawLN5Pcm3vOzCQ4jy6QUzYT7yIG7NoUxCEjtjbt3VGsUibAoGAaNLUWKTY9VaURSgqmtQS S1r13N3xupsv1k70bpiQc97LGMHb+tX2LfG03MWdMfsWRU0YBjhUHW0oF+tyFkA+TediuafJ0y KqK8INzseOQ8EIdhYCilNKIP/iyLG85EpEA+QAAAA== X-Change-ID: 20260929-cci-imp-8ba384309942 To: Robert Foss , Andi Shyti , Konrad Dybcio Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Loic Poulain , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE2MDAzMSBTYWx0ZWRfX1V4izvG5Yju9 MRQg/cBCnBAm680CnycfMGkx5Is++m34TrBipbJ+1R6FsfqXHrlnjxPRICvEydoUCmI2sEza9ch LZmZiRghAJjSHR/ETqdsvdz3AGnaHm4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE2MDAzMSBTYWx0ZWRfX9wkL1JivpE3v YDmZd727gvz4NJlXVupVqQF5xfMS7735/8oOFFoIYh19PMcx6fl+vDUPFwbB6oRA8aESnuIjp2a ktKb5IdAc97IB9Nj0R7h0MWzEDSUzoShI50IMfqW/eA9ldwYNdSTlNXI8HxlKm/1qFYNrApo8Po qRwPKEFanjXhV26hVFjIg8a35WEETfLE9MfDvBUk6XZWk6C706soembsrRQ1VjnysIqwoN2anhh /jl/qGmOx7yyslaIuMUHOdeW20UdsnDcksDydn0xkX5RFL4Xa0g+Y2Kv8MGN+LGc+qf4txPykpB meBaCgsYJqPwN75mzKSFnx9/u/NhakRmOuBVxdcbaVXyJYOx5p/xjTLMiNSa8uACMhuccDwJ9ma US4xBgujGnfKMgZ2cmBbn/AiV3TVnGg9i8jDE0r15JtwhVlINvPCRniDilXjcG8GlyaBj/cixQC Ob6bU6Rd4L+0ia7u3gw== X-Authority-Analysis: v=2.4 cv=P4yvFSAu c=1 sm=1 tr=0 ts=6ad1d98e cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=YGdjDy1V9CnC6BiKI58A:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: Dp_YpTbPqDpCROx37CFfG0pLFr569drj X-Proofpoint-GUID: Dp_YpTbPqDpCROx37CFfG0pLFr569drj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-14_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 impostorscore=0 bulkscore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610160031 Improves the Qualcomm CCI I2C driver read/write in different ways: - Capabilities (queue sizes, max transfer lengths, supported I2C mode) are currently hardcoded per DT compatible string in a handful of cci_data instances. Replace the static per-compatible structs with a single version-sorted capability catalog resolved at runtime from CCI_HW_VERSION. - The driver only supported single-command writes, capped at 11 bytes regardless of how much space the command queue actually has. Factor out the write-command queueing into a reusable helper and then add burst-write support, chunking longer writes across the whole queue instead of a single command's payload. - The FIFO read path hardcoded a fixed 12-byte limit unrelated to the actual per-revision FIFO size, with a special-cased drain loop. Simplify the FIFO read/drain loop and derive the read-side limits from each revision's FIFO size. - Add burst-read support using threshold interrupts, allowing reads of arbitrary size by draining the FIFO incrementally during the transfer. Also add overflow and underflow IRQ reporting, as queue/fifo limits are now derived from the hardware capabilities and exercised more aggressively. Unbounded writes, which refill the command queue while the transfer is still in flight and so lift the queue-depth limit on the write side, build on this series and will be posted separately. Reads up to 4 KiB and writes up to the full command queue depth (451 bytes on this part) were exercised on an imx219 behind CCI v1.8 (128-word queue, 400 kHz). Signed-off-by: Loic Poulain --- Changes in v3: - Reject a write longer than the advertised limit with an error rather than ignoring it. (Bryan) - Build the command words with FIELD_PREP() instead of open-coded shifts, which also documents the per-opcode field widths (Konrad) - Actually program CCI_IRQ_MASK_1, the RD_PAUSE bits were being ORed into the value written to CCI_IRQ_MASK_0 and so never took effect - Clear the per-transfer status on entry and stop reinitialising the completion in the read drain loop, as RD_DONE can fire while the fifo is being drained - Link to v2: https://lore.kernel.org/r/20261013-cci-imp-v2-0-6873326b44a3@oss.qualcomm.com Changes in v2: - Split the HALT_ACK reset fix out into its own patch (Andi) - Fix a typo in the "Detect capabilities from CCI_HW_VERSION" commit message (Andi) - Use GENMASK()/FIELD_GET() to decode the CCI_HW_VERSION fields (Konrad) - Derive the number of masters from the DT i2c-bus subnodes instead of encoding it per compatible string (Konrad) - Add burst read support via RD_THRESHOLD/RD_PAUSE IRQs - Link to v1: https://lore.kernel.org/r/20261004-cci-imp-v1-0-227d12cb4829@oss.qualcomm.com --- Loic Poulain (7): i2c: qcom-cci: Factor out write command queue programming i2c: qcom-cci: Handle and report queue overflow/underflow interrupts i2c: qcom-cci: Detect capabilities from CCI_HW_VERSION at runtime i2c: qcom-cci: Add burst write support i2c: qcom-cci: Extend i2c read limits based on CCI revision i2c: qcom-cci: Add burst read support i2c: qcom-cci: Build command words with FIELD_PREP() drivers/i2c/busses/i2c-qcom-cci.c | 464 +++++++++++++++++++++++++++++--------- 1 file changed, 355 insertions(+), 109 deletions(-) --- base-commit: d6dc536a4c8bb99dd822bc349a9e801be7ea81c9 change-id: 20260929-cci-imp-8ba384309942 Best regards, -- Loic Poulain