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Fri, 16 Oct 2026 01:00:15 -0700 (PDT) X-Received: by 2002:a05:620a:6844:b0:93c:6963:ff3b with SMTP id af79cd13be357-93ebd2634c9mr3364272185a.42.1792137614897; Fri, 16 Oct 2026 01:00:14 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.na.qualcomm.com ([2a01:e0a:830:450:5402:5e0b:9ef0:9b5b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48dfd4c5942sm5471446f8f.16.2026.10.16.01.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 01:00:13 -0700 (PDT) From: Loic Poulain Date: Fri, 16 Oct 2026 10:00:10 +0200 Subject: [PATCH v3 2/7] i2c: qcom-cci: Handle and report queue overflow/underflow interrupts Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261016-cci-imp-v3-2-5ee7ec1ea1a1@oss.qualcomm.com> References: <20261016-cci-imp-v3-0-5ee7ec1ea1a1@oss.qualcomm.com> In-Reply-To: <20261016-cci-imp-v3-0-5ee7ec1ea1a1@oss.qualcomm.com> To: Robert Foss , Andi Shyti , Konrad Dybcio Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Loic Poulain , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=aLdlOr9m c=1 sm=1 tr=0 ts=6ad1d990 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=L19FZshse16xndK5FkAA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: H20fnXono6N2RAcKJyxOl0J2x6eYYh90 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE2MDAzMSBTYWx0ZWRfX0j4A0p4aL3y1 vkakrGjaxdjN3Turr3HBLZUGzbIWh7EAakVvISF2IKNI0B7IGu7anRaTU5b7y6sGLuCQ8xTqcDS xG3AorHYRCeFUH9JrBHv3o9IKDwD7DM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE2MDAzMSBTYWx0ZWRfXyjpUve01oFR1 EDrdtiwfSuq8Z7e7/F+QmZQBbfUDSAJABK5A32psIKlQCysGMmSafZntFXlAidemGb5UXl4HcjX eIfHR6GFjP3URsfX1g2zpv8QHOHUgfCOi5SlRoRMwR4HzdfI/H9ZwQmlk93B0vIFpOblhSXwRFo V5dm9Vf7Xja4HkCe4BDRGL4wa3yZkOtIJKq8okDBu2My57KdKZ30kH4t57B8gvU7HH12mA/oI5O yVo+/bEWYPX5VwNx5EbKY9pJBKrmSfCk5EdRC29LorW73DZmktoDTaGP9NGc6Ztj8u6XXbZkFph uPCeF7XYopmpPmVvJwXqewVVnvzLU05U3Ma89OFAXEnLEX2zCm4L/xJiht7dxtKPToTtv0EQyhD DmCm2uBsBMDTOFseZFS7EEprjtw3c2H5XaAIcqLHDxJn1fs11lIDth++NWjexuhFNXMymkHcTlp xyCBmiHCtoxEgYJr5Rw== X-Proofpoint-GUID: H20fnXono6N2RAcKJyxOl0J2x6eYYh90 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-14_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 clxscore=1015 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610160031 CCI_IRQ_STATUS_0_I2C_Mx_ERROR aggregates the per-queue overflow and underflow bits together with NACK_ERR, and all of them were handled the same way: report -EIO and halt the queue. There was no way to tell a NACK apart from a FIFO overflow/underflow in the logs. Decode the individual overflow/underflow bits for each queue and report them with dev_warn_ratelimited() as such errors are not expected in normal operation. Signed-off-by: Loic Poulain Reviewed-by: Bryan O'Donoghue --- drivers/i2c/busses/i2c-qcom-cci.c | 34 ++++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c index 5bec317c15deddc01d3f3a6418af4164c0d56fd9..897502f55e42ddd6ea591ec756606ac07044dc0e 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -54,10 +54,18 @@ #define CCI_IRQ_STATUS_0 0xc0c #define CCI_IRQ_STATUS_0_I2C_M0_RD_DONE BIT(0) #define CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT BIT(4) +#define CCI_IRQ_STATUS_0_I2C_M0_Q0_UNDERFLOW BIT(5) +#define CCI_IRQ_STATUS_0_I2C_M0_Q0_OVERFLOW BIT(6) #define CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT BIT(8) +#define CCI_IRQ_STATUS_0_I2C_M0_Q1_UNDERFLOW BIT(9) +#define CCI_IRQ_STATUS_0_I2C_M0_Q1_OVERFLOW BIT(10) #define CCI_IRQ_STATUS_0_I2C_M1_RD_DONE BIT(12) #define CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT BIT(16) +#define CCI_IRQ_STATUS_0_I2C_M1_Q0_UNDERFLOW BIT(17) +#define CCI_IRQ_STATUS_0_I2C_M1_Q0_OVERFLOW BIT(18) #define CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT BIT(20) +#define CCI_IRQ_STATUS_0_I2C_M1_Q1_UNDERFLOW BIT(21) +#define CCI_IRQ_STATUS_0_I2C_M1_Q1_OVERFLOW BIT(22) #define CCI_IRQ_STATUS_0_RST_DONE_ACK BIT(24) #define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK BIT(25) #define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK BIT(26) @@ -190,22 +198,40 @@ static irqreturn_t cci_isr(int irq, void *dev) writel(reset, cci->base + CCI_RESET_CMD); if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_ERROR)) { + cci->master[0].status = -EIO; + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR || val & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR) cci->master[0].status = -ENXIO; - else - cci->master[0].status = -EIO; + + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_OVERFLOW) + dev_warn_ratelimited(cci->dev, "master 0 queue 0 overflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_UNDERFLOW) + dev_warn_ratelimited(cci->dev, "master 0 queue 0 underflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q1_OVERFLOW) + dev_warn_ratelimited(cci->dev, "master 0 queue 1 overflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q1_UNDERFLOW) + dev_warn_ratelimited(cci->dev, "master 0 queue 1 underflow\n"); writel(CCI_HALT_REQ_I2C_M0_Q0Q1, cci->base + CCI_HALT_REQ); ret = IRQ_HANDLED; } if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_ERROR)) { + cci->master[1].status = -EIO; + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR || val & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR) cci->master[1].status = -ENXIO; - else - cci->master[1].status = -EIO; + + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_OVERFLOW) + dev_warn_ratelimited(cci->dev, "master 1 queue 0 overflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_UNDERFLOW) + dev_warn_ratelimited(cci->dev, "master 1 queue 0 underflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q1_OVERFLOW) + dev_warn_ratelimited(cci->dev, "master 1 queue 1 overflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q1_UNDERFLOW) + dev_warn_ratelimited(cci->dev, "master 1 queue 1 underflow\n"); writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ); ret = IRQ_HANDLED; -- 2.34.1