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Tue, 25 Aug 2026 11:03:26 -0700 (PDT) X-Received: by 2002:a17:90b:4e8d:b0:38d:f5bb:e0f4 with SMTP id 98e67ed59e1d1-3966d400334mr1832233a91.1.1787681004826; Tue, 25 Aug 2026 11:03:24 -0700 (PDT) Received: from [192.168.0.7] ([49.204.110.145]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141a8f20095sm914906c88.6.2026.08.25.11.03.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Aug 2026 11:03:24 -0700 (PDT) Message-ID: <29b5226a-d403-4bdd-a114-eeb2fd341ea0@oss.qualcomm.com> Date: Tue, 25 Aug 2026 23:33:12 +0530 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 7/7] i2c: qcom-geni: Use geni_se_set_rate() for setting source clock frequency To: Mukesh Savaliya , konrad.dybcio@oss.qualcomm.com, Sudeep Holla , Cristian Marussi , Ulf Hansson , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Mark Brown , Viken Dadhaniya , Andi Shyti Cc: chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org References: <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-0-61171ab1cdce@oss.qualcomm.com> <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-7-61171ab1cdce@oss.qualcomm.com> <8af7a34a-da4f-492f-a51c-cc420edc5e6e@oss.qualcomm.com> Content-Language: en-US From: Praveen Talari In-Reply-To: <8af7a34a-da4f-492f-a51c-cc420edc5e6e@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 4hqIdD4Ho79qatd35LobGvH3pF9j6f_A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI1MDE1MyBTYWx0ZWRfX8wFFRqkJiu/H bXfyyNCc1Swgq4YdobibYcqZoVR4xXjYMXUzNes6ZT2u7I8Hub5fM4iO9MnSNZfHnphlJG5ktkX romshZBNGhasEXqhiYk3YgXNk35wJYstS9CyLC5xf/dXy9Yqt2S4Rg/JcyvOGFfSosOwQkUgJla LWBWCqkt+hRx1GQRbqH8tc8Duwsdiz1U3OZvz/+97o+23zESNjOxBrYgNXmvmGhy5Lw5AGotE5o pn6cnWwqJpalPaKpecLzsA5ffOVCoIHMqi0nu87kNBvoofBS4gRa4sJ1oRCJUaREp+jQ90WH+Df q8k2OkXAAm9aeRM81njHjOs16cR1qA9JEVOBrJQHsnLGEtV+bxPjaVpvYeB4VF5dDzeQccaGZ1k dQE8PJwD/WBpKM0UqE5zber3m28s6sk2VLQj9n7UdbxN6I15adlgxyV7r9QgaZFOsah4Jf/+dgr moeUbmkY24W+s1rHAww== X-Authority-Analysis: v=2.4 cv=ZuHd7d7G c=1 sm=1 tr=0 ts=6a8dd8ee cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=T2iwtsF3Qoe1cvxaLfjbZQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=s8i-5AHMM79FQocxpXYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI1MDE1MyBTYWx0ZWRfX+d9RSR8Kv/us ABj5lLdCCE+kT2quN+kFTayuohRPAEKpNd2HqCcYJsALZjdXkdVqnQtSwQqdo3NSfGTumr9JA4L Bg5bSOQmjtemScNVCxiUqvL74ppojFM= X-Proofpoint-ORIG-GUID: 4hqIdD4Ho79qatd35LobGvH3pF9j6f_A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-25_05,2026-08-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 adultscore=0 suspectscore=0 impostorscore=0 malwarescore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608250153 Hi Mukesh On 24-08-2026 19:11, Mukesh Savaliya wrote: > > > On 8/5/2026 1:27 AM, Praveen Talari wrote: >> On the SA8255P platform there is no Linux clock handler for the SE >> source >> clock; resources are instead managed by firmware via a genpd performance >> domain. The I2C driver therefore relies on geni_se_set_rate() to >> apply the >> fixed 19.2 MHz source clock frequency expected by the SCL divider and > > somewhere it's 32 MHz also and this may change too ? 19.2 MHz is just the frequency currently requested by the I2C driver. Other frequencies such as 32 MHz are also supported and may change in the future. > >> counter values programmed by qcom_geni_i2c_conf(). >> >> Call geni_se_set_rate() directly from qcom_geni_i2c_conf() so the >> configured frequency is applied to the correct device (the perf domain >> device on the firmware-managed path, or se->dev otherwise) without >> the I2C >> driver needing to know which resources_init() variant is in use. >> >> Drop the now-unused set_rate field from struct geni_i2c_desc, the >> geni_se_set_perf_opp() usage on the SA8255P variant, and the unused freq >> parameter from qcom_geni_i2c_conf(). >> >> Signed-off-by: Praveen Talari >> --- >>   drivers/i2c/busses/i2c-qcom-geni.c | 13 +++++++------ >>   1 file changed, 7 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c >> b/drivers/i2c/busses/i2c-qcom-geni.c >> index a23554d101fd..4561e2d235d5 100644 >> --- a/drivers/i2c/busses/i2c-qcom-geni.c >> +++ b/drivers/i2c/busses/i2c-qcom-geni.c >> @@ -213,11 +213,11 @@ static int geni_i2c_clk_map_idx(struct >> geni_i2c_dev *gi2c) >>       return -EINVAL; >>   } >>   -static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) >> +static int qcom_geni_i2c_conf(struct geni_se *se) >>   { >>       struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev); >>       const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; >> -    u32 val; >> +    u32 val, ret; >>         writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); >>   @@ -233,6 +233,10 @@ static int qcom_geni_i2c_conf(struct geni_se >> *se, unsigned long freq) >>                    itr->clk_div, itr->t_high_cnt, >>                    itr->t_low_cnt, itr->t_cycle_cnt); >>   +    ret = geni_se_set_rate(&gi2c->se, 19200000); > > hard code ? Good point. The 19.2 MHz value is not intended to be a permanent limitation. This matches the frequency currently used by the I2C driver and therefore preserves the existing behavior. If support for higher source clock frequencies (e.g. 32 MHz or others) is added in the future, the requested OPP/performance state will need to be updated accordingly. > May work currently, but if higher frequency support added, source may > change. > > Also you have added in commit message, but add a comment also here. > >> +    if (ret) >> +        return ret; >> + >>       return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, >> GENI_DEFAULT_BW, >>                     Bps_to_icc(gi2c->clk_freq_out)); >>   } > > [...] >