Re: [PATCH] powerpc: i2c-mpc: make speed registers configurable via FDT

[Timur Tabi <timur-KZfg59tc24xl57MIdRCFDg@public.gmane.org>]

Grant Likely wrote:

> No it doesn't, it depends on the register interface to decide
> compatibility.  Clock interface is part of that. 

I don't think so.  The interface for programming the clock registers is
identical on all 8[356]xx parts.  The only thing that matters is what specific
values to put in the FDR and DFSR registers to get a desired I2C bus speed.
That answer is dependent on the actual clock input to the device, which is
external to the device.  I wouldn't call the input frequency a property of the
I2C device.

> I suggested encoding
> the clock divider directly in compatible (implicit in the SoC version),
> but it doesn't have to be that way.  If clock freq is obtained from
> another property or some other method then that is okay too.

I think we agree on that.

> There is nothing wrong with it (as long as we agree and it gets
> documented).  I certainly don't have a problem with doing it this way.

I propose the property "clock-frequency", like this:

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
			clock-frequency = <0xblablabla>;  <-- added by U-Boot
		};

Note that the dfsrr property already differentiates between 8xxx and 52xx, so
maybe we don't need any other device tree changes.

-- 
Timur Tabi
Linux kernel developer at Freescale

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