From: Kenneth Heitke <kheitke-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: "Daniel Glöckner" <dg-QdrG9jWwCLEAvxtiuMwx3w@public.gmane.org>
Cc: khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org,
ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
sdharia-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
Crane Cai <crane.cai-5C7GfCeVMHo@public.gmane.org>,
Samuel Ortiz <sameo-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
Linus Walleij
<linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>,
Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>,
srinidhi kasagar
<srinidhi.kasagar-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH] i2c: Single-wire Serial Bus Interface for Qualcomm MSM chipsets
Date: Fri, 23 Jul 2010 12:32:33 -0600 [thread overview]
Message-ID: <4C49E041.8070009@codeaurora.org> (raw)
In-Reply-To: <4C496C58.1080806-QdrG9jWwCLEAvxtiuMwx3w@public.gmane.org>
Daniel Glöckner wrote:
> On 07/21/2010 07:52 PM, Kenneth Heitke wrote:
>> Unlike I2C, SSBI is a point-to-point connection, and therefore there is no
>> need to specify a slave device address. The SSBI implementation
>> overrides the slave device address to be a device register address
>> instead. This restricts the client drivers from using the SMBus
>> communication APIs unless they update the address field (addr) of the
>> i2c_client structure prior to every SMBus function call.
>
>
>> +static int
>> +i2c_ssbi_write_bytes(struct i2c_ssbi_dev *ssbi, struct i2c_msg *msg)
>> +{
>> + int ret = 0;
>> + u8 *buf = msg->buf;
>> + u16 len = msg->len;
>> + u16 addr = msg->addr;
>> +
>> + if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
>> + u32 mode2 = readl(ssbi->base + SSBI2_MODE2);
>> + writel(SSBI_MODE2_REG_ADDR_15_8(mode2, addr),
>> + ssbi->base + SSBI2_MODE2);
>> + }
>> +
>> + while (len) {
>
> Where do you set the address if controller_type == MSM_SBI_CTRL_SSBI?
>
> Daniel
>
>
The SSBI_MODE2_REG_ADDR register contains the upper 8-bits of the
address which is only supported by SSBI 2.0. The lower 8 address bits
are written as part of the SSBI_CMD_WRITE macro which is common for both
of the controller types.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2010-07-23 18:32 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-07-21 17:52 [PATCH] i2c: Single-wire Serial Bus Interface for Qualcomm MSM chipsets Kenneth Heitke
2010-07-23 10:18 ` Daniel Glöckner
[not found] ` <4C496C58.1080806-QdrG9jWwCLEAvxtiuMwx3w@public.gmane.org>
2010-07-23 18:32 ` Kenneth Heitke [this message]
2010-07-23 20:48 ` Kenneth Heitke
2010-07-23 20:50 ` Kenneth Heitke
[not found] ` <1279734768-8436-1-git-send-email-kheitke-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2010-07-28 13:26 ` Pavel Machek
[not found] ` <20100728132607.GA16737-+ZI9xUNit7I@public.gmane.org>
2010-08-10 2:26 ` Kenneth Heitke
[not found] ` <4C60B8BB.2050209-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2010-08-10 21:41 ` Pavel Machek
2010-09-24 22:48 ` Kenneth Heitke
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