* I2C controller i2c-mv64xxx.c not compliant
@ 2010-11-15 14:54 Rodolfo Giometti
[not found] ` <20101115145406.GE3372-AVVDYK/kqiJWk0Htik3J/w@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: Rodolfo Giometti @ 2010-11-15 14:54 UTC (permalink / raw)
To: mgreer-Igf4POYTYCDQT0dZR+AlfA
Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA, Mauro Barella
Hello,
I'm using a ltc4266 (PoE chip) with the Marvell i2c controller (CPU
Feroceon 88FR131).
The ltc4266 wants a repeated START during a write/read sequence,
i.e. in order to read a register with the following messages:
u8 reg = <address>;
u8 val;
struct i2c_msg msg[] = {
{ client->addr, 0, 1, ® },
{ client->addr, I2C_M_RD, 1, &val },
};
the master _must_ send a repeated START at beginning of the read
message otherwise the ltc4266 will reset its internal address register
and the master will read the register 0x00 each time!
Looking at the code the i2c-mv64xxx.c driver sends a STOP at each
message's end, but into the file include/linux/i2c.h is stated:
* Except when I2C "protocol mangling" is used, all I2C adapters implement
* the standard rules for I2C transactions. Each transaction begins with a
* START. That is followed by the slave address, and a bit encoding read
* versus write. Then follow all the data bytes, possibly including a byte
* with SMBus PEC. The transfer terminates with a NAK, or when all those
* bytes have been transferred and ACKed. If this is the last message in a
* group, it is followed by a STOP. Otherwise it is followed by the next
* @i2c_msg transaction segment, beginning with a (repeated) START.
Any suggestions in order to fix it?
Ciao,
Rodolfo
--
GNU/Linux Solutions e-mail: giometti-AVVDYK/kqiJWk0Htik3J/w@public.gmane.org
Linux Device Driver giometti-k2GhghHVRtY@public.gmane.org
Embedded Systems phone: +39 349 2432127
UNIX programming skype: rodolfo.giometti
Freelance ICT Italia - Consulente ICT Italia - www.consulenti-ict.it
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: I2C controller i2c-mv64xxx.c not compliant
[not found] ` <20101115145406.GE3372-AVVDYK/kqiJWk0Htik3J/w@public.gmane.org>
@ 2011-02-11 14:04 ` Michael Lawnick
0 siblings, 0 replies; 2+ messages in thread
From: Michael Lawnick @ 2011-02-11 14:04 UTC (permalink / raw)
To: Rodolfo Giometti, linux-i2c-u79uwXL29TY76Z2rM5mHXA
Hi Rodolfo,
Rodolfo Giometti said the following:
> I'm using a ltc4266 (PoE chip) with the Marvell i2c controller (CPU
> Feroceon 88FR131).
you already solved your issue, but where did you get register and
functional description of LTC from? Is it under NDA? I couldn't find it
in the web, just a file named 4266fa.pdf not specifying registers. Are
you willing to share your driver?
--
KR
Michael
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2011-02-11 14:04 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-11-15 14:54 I2C controller i2c-mv64xxx.c not compliant Rodolfo Giometti
[not found] ` <20101115145406.GE3372-AVVDYK/kqiJWk0Htik3J/w@public.gmane.org>
2011-02-11 14:04 ` Michael Lawnick
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).