Re: [PATCH V2 1/4] i2c: tegra: make sure register writes completes

[Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]

On 06/12/2012 04:37 AM, Laxman Dewangan wrote:
> The Tegra PPSB (an peripheral bus) queues writes transactions.
> In order to guarantee that writes have completed before a
> certain time, a read transaction to a register on the same
> bus must be executed.
> This is necessary in situations such as when clearing an
> interrupt status or enable, so that when returning from an
> interrupt handler, the HW has already de-asserted its
> interrupt status output, which will avoid spurious interrupts.
> 
> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> changes from V1:
> 	Taken care of Wolfram's review comment.

That changelog is not very descriptive. By the time a patch is reposted,
the original reviewer may well have forgotten what comments they made,
and nobody else is going to remember since they didn't make the
comments. In other words, it's better to explicitly describe the changes
that were made, rather than who requested them.