From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B2AF12CDA5; Thu, 30 Jan 2025 17:49:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738259362; cv=none; b=b1PFCf0qRxUVojZh6zLhaglHwPLvTXdWsEU52JKlDCBylepYfU4WFGduFC2phTdix01WjtnMC9feo0GORNcYvpWoPZRu5CuTMFD2ccuB7BoiAVSBe0r2v64YR2gmkZ+W6I/iHbhamevB8hPcvmTn+EyGw4Od69NKUX2Iq6iHpfM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738259362; c=relaxed/simple; bh=k/glph5Z7ozMYiVcEJWbK6kVMBSe9w2c0zCXzxWp8j0=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=EFpN5a6gwN1wLrHP0yHgUUCBDKCAubIOJrnThEku+d3ofQ0OBbjJQcXukzDQp1+R38HJD4qALpoEWXOjjAkaalwNUly+b9Mzhrua6vrOaAQcEfW7SNyflhpUWGUXIaBksr096MRb3JFQ06VgF8e3tS9DypaioCTTb7DTVoMKzqQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Zc5rXUin; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zc5rXUin" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3EC43C4CEE0; Thu, 30 Jan 2025 17:49:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738259361; bh=k/glph5Z7ozMYiVcEJWbK6kVMBSe9w2c0zCXzxWp8j0=; h=Date:Subject:To:References:From:In-Reply-To:From; b=Zc5rXUinHsm0RexQJOhCyTO5JJpNVXZS0jOlKgFNdLKZaTL/cf+EhzJCzJ2k0Ckv2 1jFSUn71jtgE7TxoYVhTWjjPXKP3oXpic0SY88p1LjSbItb0HA0RCUUW1tRZ7/FSa6 GEfMYVNYenTHdBhpxEdB4pjmDkFpim8HKFodvod654k4rrO/6p6T6XiTsSdrIIEe5x BJTl8JeyTwtYkgxFgXiAV/7UYPzudyvuCgw6ByUNp2Yxue18rBTCr+ymOtmphkysjr BvbMnmy71U9eCT19ErjoOOy7fAioqhAxj4LDy8KoFa2uHTq3MLpYEH22sYNeMLxeZ5 W8yXzrWVRcdoA== Message-ID: <4b9777cc-0bb3-44c1-92f8-209c30837f20@kernel.org> Date: Thu, 30 Jan 2025 18:49:14 +0100 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/5] i2c: tegra: Add support for SW mutex register To: Kartik Rajput , "thierry.reding@gmail.com" , Jon Hunter , Akhil R , "devicetree@vger.kernel.org" , "robh@kernel.org" , Laxman Dewangan , "krzk+dt@kernel.org" , "andi.shyti@kernel.org" , "linux-kernel@vger.kernel.org" , "conor+dt@kernel.org" , "linux-i2c@vger.kernel.org" , "digetx@gmail.com" , "linux-tegra@vger.kernel.org" References: <20250130143424.52389-1-kkartik@nvidia.com> <20250130143424.52389-5-kkartik@nvidia.com> <0daa503e73099085d84d432bb72a5f79db81a9b1.camel@nvidia.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 30/01/2025 17:35, Kartik Rajput wrote: >>>  /** >>> @@ -372,6 +382,103 @@ static void i2c_readsl(struct tegra_i2c_dev >>> *i2c_dev, void *data, >>>       readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), >>> data, len); >>>  } >>> >>> +static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, >>> +                                u32 reg, u32 mask, u32 delay_us, >>> +                                u32 timeout_us) >>> +{ >>> +     void __iomem *addr = i2c_dev->base + >>> tegra_i2c_reg_addr(i2c_dev, reg); >>> +     u32 val; >>> + >>> +     if (!i2c_dev->atomic_mode) >>> +             return readl_relaxed_poll_timeout(addr, val, !(val & >>> mask), >>> +                                               delay_us, >>> timeout_us); >>> + >>> +     return readl_relaxed_poll_timeout_atomic(addr, val, !(val & >>> mask), >>> +                                              delay_us, >>> timeout_us); >>> +} >>> + >>> +static int tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev) >>> +{ >>> +     u32 val, id; >>> + >>> +     val = i2c_readl(i2c_dev, I2C_SW_MUTEX); >>> +     id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); >>> +     if (id != 0 && id != I2C_SW_MUTEX_ID) >>> +             return 0; >>> + >>> +     val = FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID); >>> +     i2c_writel(i2c_dev, val, I2C_SW_MUTEX); >> >> And how do you exactly prevent concurrent, overwriting write? This >> looks >> like pure race. >> > > The I2C_SW_MUTEX_GRANT field reflects the id of the current mutex > owner. The I2C_SW_MUTEX_GRANT field does not change with overwrites to > the I2C_SW_MUTEX_REQUEST field, unless I2C_SW_MUTEX_REQUEST field is > cleared. So second concurrent write to I2C_SW_MUTEX_REQUEST will fail silently, and you rely on below check which ID succeeded to write? If that is how it works, then should succeed... except the trouble is that you use here i2c_readl/writel wrappers (which was already a poor idea, because it hides the implementation for no real gain) and it turns out they happen to be relaxed making all your assumptions about ordering inaccurate. You need to switch to non-relaxed API. Best regards, Krzysztof