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Wed, 21 Oct 2026 03:42:45 -0700 (PDT) X-Received: by 2002:a05:622a:1aa5:b0:52e:3991:84c8 with SMTP id d75a77b69052e-5369b5536dfmr27587491cf.2.1792579364515; Wed, 21 Oct 2026 03:42:44 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c4678faa5b0sm64563866b.37.2026.10.21.03.42.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 03:42:43 -0700 (PDT) Message-ID: <4cf59328-843a-40f4-bb9b-8fc5b9fcd574@oss.qualcomm.com> Date: Wed, 21 Oct 2026 12:42:41 +0200 X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/7] i2c: qcom-cci: Detect capabilities from CCI_HW_VERSION at runtime To: Loic Poulain , Robert Foss , Andi Shyti Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261016-cci-imp-v3-0-5ee7ec1ea1a1@oss.qualcomm.com> <20261016-cci-imp-v3-3-5ee7ec1ea1a1@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261016-cci-imp-v3-3-5ee7ec1ea1a1@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA0MiBTYWx0ZWRfX9G5G/nXHHQE5 IKdEmiBj9ZW9/tsvxKyiY7VM4CR7ncj0urQhf4EcQeC4wOXWgZCU43xakBwnIJOc6tj56/aIK0g UQfDCcBlIF52mv1reVFr5nuzJ+JgZmY= X-Proofpoint-GUID: 2QuEysiMOtPsQAPNJAsxdlq43CU6MizV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA0MiBTYWx0ZWRfXy1ZqHBMCp/xM encTo7wGCp4ZST4CyXxBTGzsSU94aXD6Myt+iEiFY/m1aDmF7M67wh6XgvwfblYZke4c+Jl44PQ 9m3vA0m9eYoN93iHckYhn31sVbvbu1ZaqfWg1sZIxMnJFX1vjs5CvO8iL+fGenhOIAgYLrCTLtw m0WEBjXjOJs6ZhvAYFaztNry73bshBJZ0roUoMDy+ZdlX/jkHZMaMpEUOzSkDZs13BUz6bPUrTU Agc3yYKKehhAGrgmOWA7BsLpXoRWL1mcMrIdmQiwQgOBGMAeg8HuztPF7eRgpWdc+0jilNU8yTp D0ch+b0IJS/jkSiTCL6NEsDwHP66+CUKBdNgYj87f7ueM6ckfkN6vbrrAkL4UOVJheqnFHwBxgG 0YD0M6lZ+0V580X0TkWz7hQV14IQp5FJ/tFcyLf9xbuwdRavDutgqtH5E9EEpB9d7Pa4WBOpxOZ amqcePLw1xAyun/ktVw== X-Authority-Analysis: v=2.4 cv=R42WitRX c=1 sm=1 tr=0 ts=6ad89725 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=NORypjkHWnF_li2zo8gA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-ORIG-GUID: 2QuEysiMOtPsQAPNJAsxdlq43CU6MizV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_03,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 spamscore=0 malwarescore=0 adultscore=0 clxscore=1015 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210042 On 10/16/26 10:00 AM, Loic Poulain wrote: > In theory, every SoC integrating a CCI revision that differs from > an existing one should introduce a dedicated compatible string. > In practice, most CCI instances still fall back to the msm8996 > compat (v1.4.0), one of the oldest supported versions. In order > to take advantage of capabilities introduced in later versions, > such as larger queues (v1.6.0) or threshold IRQ support (v1.7.0), > we need to properly distinguish the different variants. > > Replace the static per-compatible cci_data definitions with a > version-sorted capability table keyed by (hw_major, hw_minor). > During probe, read CCI hardware revision register and select > the newest capability entry whose version is less than or equal > to the detected hardware revision. This allows revisions to > automatically inherit the closest supported capability set > without requiring additional compatible strings. > > Several compatibles that currently fall back to the msm8996 > configuration (e.g. sdm845, sm8250 and sm8450) will now resolve > to the corresponding capability tier, gaining access to their > larger queue sizes instead of the conservative msm8996 defaults. > > - v1.2.x CCI increase I2C write payload + burst write support > - v1.6.x CCI has increased queue sizes (64,16) -> (128,32) > - v1.7.x CCI introduces threshold IRQs (leveraged later) > - v1.10.x CCI increase queue 0 size (128) -> (1024) > > Suggested-by: Konrad Dybcio > Signed-off-by: Loic Poulain > --- Reviewed-by: Konrad Dybcio Konrad