Re: [PATCH 1/1] i2c: omap: correct usage of the interrupt enable register

[Oleksandr Dmytryshyn <oleksandr.dmytryshyn-l0cyMroinI0@public.gmane.org>]

On 05/29/2013 08:22 PM, Kevin Hilman wrote:
> Oleksandr Dmytryshyn <oleksandr.dmytryshyn-l0cyMroinI0@public.gmane.org> writes:
>
>> Starting from the OMAP chips with version2 registers scheme there are
>> 2 registers (I2C_IRQENABLE_SET and I2C_IRQENABLE_CLR) to manage
>> interrupts instead of the older OMAP chips with old scheme which have
>> only one register (I2C_IE).  Now we should use I2C_IRQENABLE_SET
>> register for enabling interrupts and I2C_IRQENABLE_CLR register for
>> disabling interrupts.
> Why?  (changelogs should always answer the "why" question)
>
> IOW, what is broken without this change, how does it fail?  And equally
> important, how is it currently working?
>
> Kevin
>
>
Hi, Kevin.

If the i2c controller during suspend will generate an interrupt, it can 
lead to unpredictable behaviour in the kernel.

Based on the logic of the kernel code interrupts from i2c should be 
prohibited during suspend. Kernel writes 0 to the I2C_IE register in the 
omap_i2c_runtime_suspend() function. In the other side kernel writes 
saved interrupt flags to the I2C_IE register in 
omap_i2c_runtime_resume() function. I.e. interrupts should be disabled 
during suspend.

This works for chips with version1 registers scheme. Interrupts are 
disabled during suspend. For chips with version2 scheme registers 
writting 0 to the I2C_IE register does nothing (because now the 
I2C_IRQENABLE_SET register is located at this address ). This register 
is used to enable interrupts. For disabling interrupts I2C_IRQENABLE_CLR 
register should be used.

I've checked that interrupts in the i2c controller are still enabled 
after writting 0 to the I2C_IE register. But with my patch interrupts 
are disabled in the omap_i2c_runtime_suspend() function.

-- 

Best regards,
Oleksandr Dmytryshyn | OMAP4 Platform
GlobalLogic Inc. | Innovation by Design