From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime COQUELIN Subject: Re: [PATCH v4 3/4] ARM: STi: Supply I2C configuration to STiH415 SoC Date: Thu, 10 Oct 2013 14:49:45 +0200 Message-ID: <5256A269.9070809@st.com> References: <1381250576-7916-1-git-send-email-maxime.coquelin@st.com> <1381250576-7916-4-git-send-email-maxime.coquelin@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7BIT Return-path: In-Reply-To: Content-Language: en-US Sender: linux-i2c-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Stephen GALLIMORE , Wolfram Sang , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" Cc: Stuart MENEFY , Lee Jones , Gabriel FERNANDEZ , Srinivas KANDAGATLA List-Id: linux-i2c@vger.kernel.org On 10/10/2013 02:33 PM, Stephen GALLIMORE wrote: >> -----Original Message----- >> From: Maxime COQUELIN [mailto:maxime.coquelin-qxv4g6HH51o@public.gmane.org] >> Sent: 08 October 2013 17:43 >> ..... >> + >> + i2c@fed40000 { >> + compatible = "st,comms-ssc-i2c"; >> + reg = <0xfed40000 0x110>; >> + interrupts = ; > This should specify level (high) triggered, not edge triggered, for our > SoC integrations. > > Note that level triggered is the default GIC setup and was therefore > what was being used when you specified "0" for the flags previously. Thanks Stephen. As discussed this morning, I agree this should be high level triggered. This will be fixed in next revision. > >> + clocks = <&CLKS_ICN_REG_0>; >> + clock-names = "ssc"; >> + clock-frequency = <400000>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_i2c0_default>; >> + >> + status = "disabled"; >> + };