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From: alfred steele <alfred.jaquez-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: i2c driver for mxc platform
Date: Mon, 15 Mar 2010 13:00:42 -0500	[thread overview]
Message-ID: <528f13591003151100q29984964n99828cccad075d41@mail.gmail.com> (raw)

Hi ,


Looks like there is some discrepancy with the mxc i2c driver.

In this portion of the mxc_i2c_stop()  routine, the MSTA bit is
cleared(1to 0) to generate a stop condition but there is no  state
check whatsoever before for the IBB bit (bus busy bit is set or not)

while (retry-- && ((sr & MXC_I2SR_IBB))) {
        udelay(3);
        sr = readw(dev->membase + MXC_I2SR);

I am not sure what SCL frequency has been tested with  for the
"udelay(3)". Is that a sufficient wait on busses set to run on the
traditional slow rate(bit rate upto 100 kbps?

I am curious.

Thanks,
Alfred.

             reply	other threads:[~2010-03-15 18:00 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-03-15 18:00 alfred steele [this message]
     [not found] ` <528f13591003151100q29984964n99828cccad075d41-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2010-03-15 19:37   ` i2c driver for mxc platform Robert Schwebel

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