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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-33b61aab6c1sm17809395a91.13.2025.10.14.20.41.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Oct 2025 20:41:07 -0700 (PDT) Message-ID: <53ae7338-e5db-40dd-9fac-f06a97584cef@oss.qualcomm.com> Date: Wed, 15 Oct 2025 11:41:02 +0800 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/6] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY To: Bryan O'Donoghue , Jingyi Wang , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com References: <20250924-knp-cam-v1-0-b72d6deea054@oss.qualcomm.com> <9cVxYzExtV_uysqXmZcP03jBKVwb9fRH7EuJPSeLUS-Juqq3JdoISB_wwBeiJUTBFr0ZuGTg2sSXn8NjSi11Pg==@protonmail.internalid> <20250924-knp-cam-v1-4-b72d6deea054@oss.qualcomm.com> Content-Language: en-US From: Hangxiang Ma In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 0NBGv7EjZftOSFljWQxSuQWgPrJglRUT X-Authority-Analysis: v=2.4 cv=e5MLiKp/ c=1 sm=1 tr=0 ts=68ef17d6 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=9dEm_Dpkgd8kDuDKjw8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE0MDEzNCBTYWx0ZWRfX0fCtA8xl+jH3 hIaZRU2QyR9ntNpJ5f82wM71i3OcKDdC2TppgbfXntG1ejMyeVqxyjvZAyxGOcC9uQFilxQS7QM l8rdpcEn6GbV3tXhtXvLl4erIuu76qk33h8AG4U2cUPpyssNoAGXH0wH6XdJ4mM+r3V/PYx/g86 YkDDMnRTvwRYrq2EY+1oktfp6SSNjIjNKC7Hrjt4HEXH39r7MsmY+VBp9wqT5q7CWHSPyxUrH1K dZc/3ZAZ69vS8YChjhld5dGAWDjR6+AcpOo/h+iIzj1Kr/boymOR5baIejE/Vfs6TYxGPwX3YYH Uxk9xKZmygm8IMdU4p1XGMlWBIpm7+jjuyY0NBUsefg29+7GIht/Ai371kEJWqrIviExsbp9W6+ Ri8Isi+PdAI61Tr0199Q3nOyIsPS1A== X-Proofpoint-ORIG-GUID: 0NBGv7EjZftOSFljWQxSuQWgPrJglRUT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-15_01,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510140134 On 9/25/2025 8:57 PM, Bryan O'Donoghue wrote: > On 25/09/2025 01:02, Jingyi Wang wrote: >> From: Hangxiang Ma >> >> Add more detailed resource information for CSIPHY devices in the camss >> driver along with the support for v2.4.0 in the 2 phase CSIPHY driver >> that is responsible for the PHY lane register configuration, module >> reset and interrupt handling. >> >> This change adds 'cmn_status_offset' variable in 'csidphy_device_regs' >> structure. It helps adapt the offset to the common status registers that >> is different in v2.4.0 from others. >> >> Signed-off-by: Hangxiang Ma >> Signed-off-by: Jingyi Wang >> --- >>   .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 138 >> ++++++++++++++++++++- >>   drivers/media/platform/qcom/camss/camss-csiphy.h   |   1 + >>   drivers/media/platform/qcom/camss/camss.c          | 107 >> ++++++++++++++++ >>   3 files changed, 240 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c >> b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c >> index a229ba04b158..ecb91d3688ca 100644 >> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c >> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c >> @@ -46,7 +46,7 @@ >>   #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE    BIT(7) >>   #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) >>   #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID    BIT(1) >> -#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + >> 0xb0 + 0x4 * (n)) >> +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, bias, n) ((offset) >> + (bias) + 0x4 * (n)) > > You need to explain this bias parameter in the commit log. Ack. Now rename the 'bias' parameter the same as 'common_status_offset' to remove ambiguity. >> >>   #define CSIPHY_DEFAULT_PARAMS        0 >>   #define CSIPHY_LANE_ENABLE        1 >> @@ -587,6 +587,123 @@ csiphy_lane_regs lane_regs_sm8550[] = { >>       {0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, >>   }; >> >> +/* GEN2 2.4.0 2PH DPHY mode */ > > You need to call out the process node in this comment, per the other > recent additions. Ack >> +static const struct >> +csiphy_lane_regs lane_regs_kaanapali[] = { >> +    /* LN 0 */ >> +    {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0000, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, >> +    {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL}, >> +    {0x005C, 0x54, 0x00, CSIPHY_SKEW_CAL}, >> +    {0x0060, 0xFD, 0x00, CSIPHY_SKEW_CAL}, >> +    {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, >> + >> +    /* LN 2 */ >> +    {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0400, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, >> +    {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL}, >> +    {0x045C, 0x54, 0x00, CSIPHY_SKEW_CAL}, >> +    {0x0460, 0xFD, 0x00, CSIPHY_SKEW_CAL}, >> +    {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, >> + >> +    /* LN 4 */ >> +    {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0800, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, >> +    {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL}, >> +    {0x085C, 0x54, 0x00, CSIPHY_SKEW_CAL}, >> +    {0x0860, 0xFD, 0x00, CSIPHY_SKEW_CAL}, >> +    {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL}, >> + >> +    /* LN 6 */ >> +    {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C00, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, >> +    {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL}, >> +    {0x0C5C, 0x54, 0x00, CSIPHY_SKEW_CAL}, >> +    {0x0C60, 0xFD, 0x00, CSIPHY_SKEW_CAL}, >> +    {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL}, >> + >> +    /* LN CLK */ >> +    {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +    {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, >> +    {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, >> +}; >> + >>   /* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */ >>   static const struct >>   csiphy_lane_regs lane_regs_x1e80100[] = { >> @@ -714,13 +831,13 @@ static void csiphy_hw_version_read(struct >> csiphy_device *csiphy, >>              CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6)); >> >>       hw_version = readl_relaxed(csiphy->base + >> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 12)); >> +        CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, >> regs->cmn_status_offset, 12)); >>       hw_version |= readl_relaxed(csiphy->base + >> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 13)) << 8; >> +        CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, >> regs->cmn_status_offset, 13)) << 8; >>       hw_version |= readl_relaxed(csiphy->base + >> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 14)) << 16; >> +        CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, >> regs->cmn_status_offset, 14)) << 16; >>       hw_version |= readl_relaxed(csiphy->base + >> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 15)) << 24; >> +        CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, >> regs->cmn_status_offset, 15)) << 24; >> >>       dev_dbg(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version); >>   } >> @@ -749,7 +866,8 @@ static irqreturn_t csiphy_isr(int irq, void *dev) >>       for (i = 0; i < 11; i++) { >>           int c = i + 22; >>           u8 val = readl_relaxed(csiphy->base + >> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, i)); >> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, >> +                              regs->cmn_status_offset, i)); >> >>           writel_relaxed(val, csiphy->base + >> CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, c)); >> @@ -915,6 +1033,7 @@ static bool csiphy_is_gen2(u32 version) >>       case CAMSS_845: >>       case CAMSS_8550: >>       case CAMSS_8775P: >> +    case CAMSS_KAANAPALI: >>       case CAMSS_X1E80100: >>           ret = true; >>           break; >> @@ -989,6 +1108,7 @@ static int csiphy_init(struct csiphy_device >> *csiphy) >> >>       csiphy->regs = regs; >>       regs->offset = 0x800; >> +    regs->cmn_status_offset = 0xb0; >> >>       switch (csiphy->camss->res->version) { >>       case CAMSS_845: >> @@ -1023,6 +1143,12 @@ static int csiphy_init(struct csiphy_device >> *csiphy) >>           regs->lane_regs = &lane_regs_sa8775p[0]; >>           regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p); >>           break; >> +    case CAMSS_KAANAPALI: >> +        regs->lane_regs = &lane_regs_kaanapali[0]; >> +        regs->lane_array_size = ARRAY_SIZE(lane_regs_kaanapali); >> +        regs->offset = 0x1000; >> +        regs->cmn_status_offset = 0x138; > > I don't think a second offset is warranted > > You could acheive the required offset with offset = 0x1138; and a > comment. > > Perhaps I'm not seeing it but seems like an additional - fixed - fluff > variable. Necessary to add another variable here. The 'offset' parameter denotes the address offset between base and the common register. But the 'common_status_offset' denotes the offset between common registers and status registers.