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Tue, 18 Aug 2026 05:16:14 -0700 (PDT) X-Received: by 2002:a05:620a:28d0:b0:936:6e2f:a34d with SMTP id af79cd13be357-936d25c59f5mr2262517885a.3.1787055373636; Tue, 18 Aug 2026 05:16:13 -0700 (PDT) Received: from [192.168.120.193] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c217fed830csm170702166b.26.2026.08.18.05.16.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Aug 2026 05:16:12 -0700 (PDT) Message-ID: <5a7ecb83-a01c-4136-bffa-96c64e77c5e9@oss.qualcomm.com> Date: Tue, 18 Aug 2026 14:16:10 +0200 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/5] i2c: qcom-cci: Enforce the required CCI clock rate To: Loic Poulain , Robert Foss , Andi Shyti , Wolfram Sang , Dmitry Baryshkov , Luca Weiss Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, vladimir.zapolskiy@linaro.org, konradybcio@kernel.org, stephan.gerhold@linaro.org, Wenmeng Liu References: <20260801-cci-clk-fix-v4-0-e1d80da54e01@oss.qualcomm.com> <20260801-cci-clk-fix-v4-5-e1d80da54e01@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260801-cci-clk-fix-v4-5-e1d80da54e01@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: TE_88zR9moKCcWYw5hGhqf3ojiTPGMnx X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE4MDA4OSBTYWx0ZWRfX1FDV+BWl4ECi 8yFtToyrzcmLp2pSubPG6xamhoHwQQH2ox6JKUfCkEuMUZNDEpGLmDIvGCqmqeSKqebJq6c3jFs Nrx5OU7peGU2yIEzCBjtNRE9vguLfGjy5lAoR3ClUZ16qBHs05+814CpKq1KIcvplQ7bn9k+c80 4jcV9L5n7C+/pCucoD3Aa7aEeJuQit33aF6QGWWIKhIijL3JE9NGM7Kt36meBifYYjIYSJW8O/2 lclpQJY369rU8ZuGPuBQ92KWBVpBectGrmxiFZ6UxXdooGQi+wx0A/sm0XwLDKFusFZjx4hJW2+ H3ItPwg0kzOqs9vjnQkZPmiz3nxcu+90W7IduSLC/13AkVneY+gJCPWdAaht+Bzq0Yy4Hl/9Fh8 C1amjtdYvI7cWFBzi9E5gYINP4jHp56cp/ddcZ9TUrFu1p0+h+ATI0/ZQxO1vAf/JOfRjnlCoEF v+tHOSwBCYpp8w/ciHA== X-Proofpoint-Spam-Info: AW1haW4tMjYwODE4MDA4OSBTYWx0ZWRfX3/RTvVwBxuns 7AcNiRbpPbqACQLGMjUwAA9Xxe+lf9d5x+3VIZUgcuEROpWEjVKC9XKrwEL2M/SvZ5dvMX/1GdP ROTam/gf4ycf9i/W//l9gifMHO7Q+KY= X-Authority-Analysis: v=2.4 cv=FsU1OWrq c=1 sm=1 tr=0 ts=6a844d0e cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=l0ArfioIlEm0Nh1NdZUA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: TE_88zR9moKCcWYw5hGhqf3ojiTPGMnx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-18_01,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 phishscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608180089 On 8/1/26 10:10 PM, Loic Poulain wrote: > The CCI hw_params timing values are only valid at the specific clock > rate they were calibrated for. A previous change made the driver select > the timing set matching the currently running clock rate, but the rate > itself was still left to the DT (assigned-clock-rates) or the bootloader, > which is fragile: if no rate is enforced the timings may not match and > violate the I2C specification. [...] > +/* > + * The single CCI clock is shared by all masters, which may run in different > + * modes. Pick the lowest rate that has a valid timing set for every active > + * master's mode.> + */ > +static unsigned long cci_get_required_rate(struct cci *cci) > +{ > + int ri, i; Please declare the loop iterators in the loop 'header', it's been OKd inside the kernel for a while now > + > + for (ri = 0; ri < NUM_CCI_CLK_RATES; ri++) { > + bool supported = true; > + > + for (i = 0; i < cci->data->num_masters; i++) { > + int mode = cci->master[i].mode; > + > + if (!cci->master[i].cci) > + continue; > + > + if (mode > cci->data->max_mode || > + !cci_hw_params[ri][mode].thigh) { > + supported = false; > + break; > + } This still goes to dev_pm_opp_set_rate() with a value of 0, which is BAD - let's check the retval of this function and pass the rate via a pointer parameter > + } > + > + if (supported) > + return cci_clk_rates[ri]; > + } > + > + return 0; > +} > + > +static int cci_set_core_rate(struct cci *cci, unsigned long rate) > +{ > + struct device *dev = cci->dev; > + int ret; > + > + ret = dev_pm_opp_set_rate(dev, rate); > + if (ret) { > + dev_warn(dev, "CCI clock could not be set to %lu Hz\n", rate); > + return ret; > + } > + > + if (!rate) > + return 0; > + > + /* > + * Sanity: The hw_params timings are only valid at the exact > + * expected rate, verify what landed on the hardware. > + */ > + if (clk_get_rate(cci->cci_clk) != rate) > + dev_warn(dev, "CCI clock is not at expected %lu Hz\n", rate); > + > + return 0; > +} > + > static int __maybe_unused cci_suspend_runtime(struct device *dev) > { > struct cci *cci = dev_get_drvdata(dev); > > + cci_set_core_rate(cci, 0); No, that's a footgun https://lore.kernel.org/linux-arm-msm/20260728-topic-dpu_power-v1-0-e7783b859a70@oss.qualcomm.com/ > cci_disable_clocks(cci); > return 0; > } > @@ -588,6 +646,10 @@ static int __maybe_unused cci_resume_runtime(struct device *dev) > struct cci *cci = dev_get_drvdata(dev); > int ret; > > + ret = cci_set_core_rate(cci, cci_get_required_rate(cci)); > + if (ret) > + return ret; You generally only need to set_rate once and then enable/disable the clocks, so this can be removed Konrad