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Wed, 08 Jul 2026 02:23:57 -0700 (PDT) X-Received: by 2002:a05:6a00:6f0f:b0:848:4d1a:9554 with SMTP id d2e1a72fcca58-8484d1a9805mr155938b3a.38.1783502637009; Wed, 08 Jul 2026 02:23:57 -0700 (PDT) Received: from [10.218.14.97] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-847f6ddc974sm6870170b3a.60.2026.07.08.02.23.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Jul 2026 02:23:56 -0700 (PDT) Message-ID: <5d206010-a35e-460d-9b11-7dbaa8a56add@oss.qualcomm.com> Date: Wed, 8 Jul 2026 14:53:52 +0530 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] i2c: qcom-geni: use dedicated completions for abort and reset events To: Mukesh Savaliya , Viken Dadhaniya , Andi Shyti Cc: linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, Naresh Maramaina References: <20260708-fix_cancel_sequence_on_failure_for_i2c-v1-0-dd8f841f36a2@oss.qualcomm.com> <20260708-fix_cancel_sequence_on_failure_for_i2c-v1-2-dd8f841f36a2@oss.qualcomm.com> <6167cdea-50d0-4319-9f4d-1f1b349600df@oss.qualcomm.com> Content-Language: en-US From: Praveen Talari In-Reply-To: <6167cdea-50d0-4319-9f4d-1f1b349600df@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: QayiDt0i9hsLaRjfUkLqBdBnBbYEBkq_ X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA4MDA5MCBTYWx0ZWRfX8TpiynFhs3NI iqFx4b0iDS8q8/nGGj+3j7hTcCWJtE8QXQNyip4v2suY6nbodwT+Pm2asTsKgiOs9mT7OfSR1NR zy4eY7QxzvQbVkhcL9c9mw3iJN3jh3E= X-Authority-Analysis: v=2.4 cv=CNoamxrD c=1 sm=1 tr=0 ts=6a4e172e cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=KqGaXZP3fpkHBQvqf4kA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: QayiDt0i9hsLaRjfUkLqBdBnBbYEBkq_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA4MDA5MCBTYWx0ZWRfX9IMfPL/JrVd+ Gxw3kqX1V7rYbCS7Uz5D2yKg9RQvGZFv1oplgU0NDQmz3tVV2H+tDHTSlOPe9rtm8a0vv76RzC0 smtyoP7EkUxUeRT8zeJn0qcHkX/Zhax/qAeA7dGNlWc2xRC5j3QRUVC8gqbFYmrNw8s6N3228qf elwoLaejShscqmyIYEVogMRcfSxOZpo3UwgkrzYCWMdkd+ezsNS8c0zFGhsCPB0iVuhRAchifkk ni9aJ86WOW536wU9KSn7gn/XtojxsnD7pUD4/uz0yzmuE5jdevZSFaVrUXH1HiMVnejUVnsQRlT KDrDwpdt4ORrtaw2VKvdJy4ngp04OaEGbzzWCuMdH+jLRdsShNNSxni1IWJYyOBkFzLVKl0RDCp E877RoO1eOiwYKHlr9Ss67XEfp111rBs3m9jngf/paSrYbE8X9As2J1r0vvFJXuLKRffnftoxHN 1pzo20EsdT8GtE6DFnw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-08_01,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 adultscore=0 phishscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607080090 Hi Mukesh, On 08-07-2026 13:05, Mukesh Savaliya wrote: > > > On 7/8/2026 11:45 AM, Praveen Talari wrote: >> The driver uses the shared gi2c->done completion for transfer, abort, > shared => common completion event for transfer, abort and DMA reset Sure. >> and DMA reset operations. This allows unrelated completion events to >> prematurely wake abort and reset waiters, leading to incorrect >> synchronization. > Aren't they in sequence i.e. one after another ? If the IRQ is triggered late, it can impact the subsequent transfer because gi2c->done may be cleared before the delayed interrupt is handled. >> >> Introduce dedicated completions for abort, TX reset, and RX reset >> operations, and signal them only from their respective interrupt >> events. This removes the dependency on shared completion state and >> eliminates the abort_done flag-based synchronization. >> >> Co-developed-by: Naresh Maramaina >> Signed-off-by: Naresh Maramaina >> Signed-off-by: Praveen Talari >> --- >>   drivers/i2c/busses/i2c-qcom-geni.c | 54 >> +++++++++++++++++++------------------- >>   1 file changed, 27 insertions(+), 27 deletions(-) >> >> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c >> b/drivers/i2c/busses/i2c-qcom-geni.c >> index 15403edb355a..9490aee4928c 100644 >> --- a/drivers/i2c/busses/i2c-qcom-geni.c >> +++ b/drivers/i2c/busses/i2c-qcom-geni.c >> @@ -113,7 +113,10 @@ struct geni_i2c_dev { >>       int err; >>       struct i2c_adapter adap; >>       struct completion done; >> +    struct completion abort_done; >>       struct completion cancel_done; >> +    struct completion tx_reset_done; >> +    struct completion rx_reset_done; > tx or rx, any one would be running. Not both right ? > if so, i suggest to keep common dma_reset_done. As explained above, there is a possibility that a delayed IRQ may occur while another reset operation is still in progress, potentially affecting the reset sequence. Thanks, Praveen Talari >>       struct i2c_msg *cur; >>       int cur_wr; >>       int cur_rd; >> @@ -127,7 +130,6 @@ struct geni_i2c_dev { > [..] >