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[82.149.19.102]) by smtp.gmail.com with ESMTPSA id 8-20020a170906300800b0073dd8e5a39fsm3664768ejz.156.2022.11.07.10.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 10:00:11 -0800 (PST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Chen-Yu Tsai , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Andre Przywara Cc: =?ISO-8859-1?Q?Cl=E9ment_P=E9ron?= , Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-i2c@vger.kernel.org Subject: Re: [PATCH v2 03/10] ARM: dts: suniv: f1c100s: add I2C DT nodes Date: Mon, 07 Nov 2022 19:00:10 +0100 Message-ID: <7447015.EvYhyI6sBW@kista> In-Reply-To: <20221107005433.11079-4-andre.przywara@arm.com> References: <20221107005433.11079-1-andre.przywara@arm.com> <20221107005433.11079-4-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Dne ponedeljek, 07. november 2022 ob 01:54:26 CET je Andre Przywara napisal(a): > The Allwinner F1C100s series of SoCs contain three I2C controllers > compatible to the ones used in other Allwinner SoCs. > > Add the DT nodes describing the resources of the controllers. > I2C1 has only one possible pinmux, so add the pinctrl properties for > that already. Above statement doesn't match current changes anymore. With that removed: Reviewed-by: Jernej Skrabec If nothing else pops up, I can fix this while applying. Best regards, Jernej > At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so > include those pins already, to simplify referencing them later. > > Signed-off-by: Andre Przywara > --- > arch/arm/boot/dts/suniv-f1c100s.dtsi | 42 ++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi > b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 81749d5da12f..4f45168cea42 > 100644 > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi > @@ -192,6 +192,12 @@ mmc0_pins: mmc0-pins { > drive-strength = <30>; > }; > > + /omit-if-no-ref/ > + i2c0_pd_pins: i2c0-pd-pins { > + pins = "PD0", "PD12"; > + function = "i2c0"; > + }; > + > spi0_pc_pins: spi0-pc-pins { > pins = "PC0", "PC1", "PC2", "PC3"; > function = "spi0"; > @@ -203,6 +209,42 @@ uart0_pe_pins: uart0-pe-pins { > }; > }; > > + i2c0: i2c@1c27000 { > + compatible = "allwinner,suniv-f1c100s-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x01c27000 0x400>; > + interrupts = <7>; > + clocks = <&ccu CLK_BUS_I2C0>; > + resets = <&ccu RST_BUS_I2C0>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c1: i2c@1c27400 { > + compatible = "allwinner,suniv-f1c100s-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x01c27400 0x400>; > + interrupts = <8>; > + clocks = <&ccu CLK_BUS_I2C1>; > + resets = <&ccu RST_BUS_I2C1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c2: i2c@1c27800 { > + compatible = "allwinner,suniv-f1c100s-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x01c27800 0x400>; > + interrupts = <9>; > + clocks = <&ccu CLK_BUS_I2C2>; > + resets = <&ccu RST_BUS_I2C2>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > timer@1c20c00 { > compatible = "allwinner,suniv-f1c100s- timer"; > reg = <0x01c20c00 0x90>; > -- > 2.35.5