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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 12:35:29.5193 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a71a21e-709e-4778-1a5a-08da65955633 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4206 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org On 7/14/22 13:58, Datta, Shubhrajyoti wrote: > [AMD Official Use Only - General] > > Hi , > >> -----Original Message----- >> From: Robert Hancock >> Sent: Wednesday, June 15, 2022 4:59 AM >> To: linux-i2c@vger.kernel.org >> Cc: Raviteja Narayanam ; Michal Simek >> ; Anurag Kumar Vulisha ; >> wsa@kernel.org; Shubhrajyoti Datta ; Robert >> Hancock >> Subject: [PATCH] i2c: cadence: Change large transfer count reset logic to be >> unconditional >> >> Problems were observed on the Xilinx ZynqMP platform with large I2C reads. >> When a read of 277 bytes was performed, the controller NAKed the transfer >> after only 252 bytes were transferred and returned an ENXIO error on the >> transfer. >> >> There is some code in cdns_i2c_master_isr to handle this case by resetting >> the transfer count in the controller before it reaches 0, to allow larger >> transfers to work, but it was conditional on the >> CDNS_I2C_BROKEN_HOLD_BIT quirk being set on the controller, and ZynqMP >> uses the r1p14 version of the core where this quirk is not being set. The >> requirement to do this to support larger reads seems like an inherently >> required workaround due to the core only having an 8-bit transfer size >> register, so it does not appear that this should be conditional on the broken >> HOLD bit quirk which is used elsewhere in the driver. >> >> Remove the dependency on the CDNS_I2C_BROKEN_HOLD_BIT for this >> transfer size reset logic to fix this problem. >> > Reviewed-by Shubhrajyoti Datta > >> Fixes: 63cab195bf49 ("i2c: removed work arounds in i2c driver for Zynq >> Ultrascale+ MPSoC") >> Signed-off-by: Robert Hancock >> --- Acked-by: Michal Simek Thanks, Michal