Re: [PATCH v1 2/6] dt-bindings: i2c: convert ocores binding to yaml

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 05/06/2022 15:32, mail@conchuod.ie wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Convert the open cores i2c controller binding from text to yaml.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../devicetree/bindings/i2c/i2c-ocores.txt    |  78 -----------
>  .../devicetree/bindings/i2c/i2c-ocores.yaml   | 132 ++++++++++++++++++
>  2 files changed, 132 insertions(+), 78 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-ocores.txt
>  create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ocores.yaml
> 
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> deleted file mode 100644
> index a37c9455b244..000000000000
> --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> +++ /dev/null
> @@ -1,78 +0,0 @@
> -Device tree configuration for i2c-ocores
> -
> -Required properties:
> -- compatible      : "opencores,i2c-ocores"
> -                    "aeroflexgaisler,i2cmst"
> -                    "sifive,fu540-c000-i2c", "sifive,i2c0"
> -                    For Opencore based I2C IP block reimplemented in
> -                    FU540-C000 SoC.
> -                    "sifive,fu740-c000-i2c", "sifive,i2c0"
> -                    For Opencore based I2C IP block reimplemented in
> -                    FU740-C000 SoC.
> -                    Please refer to sifive-blocks-ip-versioning.txt for
> -                    additional details.
> -- reg             : bus address start and address range size of device
> -- clocks          : handle to the controller clock; see the note below.
> -                    Mutually exclusive with opencores,ip-clock-frequency
> -- opencores,ip-clock-frequency: frequency of the controller clock in Hz;
> -                    see the note below. Mutually exclusive with clocks
> -- #address-cells  : should be <1>
> -- #size-cells     : should be <0>
> -
> -Optional properties:
> -- interrupts      : interrupt number.
> -- clock-frequency : frequency of bus clock in Hz; see the note below.
> -                    Defaults to 100 KHz when the property is not specified
> -- reg-shift       : device register offsets are shifted by this value
> -- reg-io-width    : io register width in bytes (1, 2 or 4)
> -- regstep         : deprecated, use reg-shift above
> -
> -Note
> -clock-frequency property is meant to control the bus frequency for i2c bus
> -drivers, but it was incorrectly used to specify i2c controller input clock
> -frequency. So the following rules are set to fix this situation:
> -- if clock-frequency is present and neither opencores,ip-clock-frequency nor
> -  clocks are, then clock-frequency specifies i2c controller clock frequency.
> -  This is to keep backwards compatibility with setups using old DTB. i2c bus
> -  frequency is fixed at 100 KHz.
> -- if clocks is present it specifies i2c controller clock. clock-frequency
> -  property specifies i2c bus frequency.
> -- if opencores,ip-clock-frequency is present it specifies i2c controller
> -  clock frequency. clock-frequency property specifies i2c bus frequency.
> -
> -Examples:
> -
> -	i2c0: ocores@a0000000 {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		compatible = "opencores,i2c-ocores";
> -		reg = <0xa0000000 0x8>;
> -		interrupts = <10>;
> -		opencores,ip-clock-frequency = <20000000>;
> -
> -		reg-shift = <0>;	/* 8 bit registers */
> -		reg-io-width = <1>;	/* 8 bit read/write */
> -
> -		dummy@60 {
> -			compatible = "dummy";
> -			reg = <0x60>;
> -		};
> -	};
> -or
> -	i2c0: ocores@a0000000 {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		compatible = "opencores,i2c-ocores";
> -		reg = <0xa0000000 0x8>;
> -		interrupts = <10>;
> -		clocks = <&osc>;
> -		clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
> -
> -		reg-shift = <0>;	/* 8 bit registers */
> -		reg-io-width = <1>;	/* 8 bit read/write */
> -
> -		dummy@60 {
> -			compatible = "dummy";
> -			reg = <0x60>;
> -		};
> -	};
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.yaml b/Documentation/devicetree/bindings/i2c/i2c-ocores.yaml
> new file mode 100644
> index 000000000000..1693ffffbe31
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.yaml
> @@ -0,0 +1,132 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/i2c/i2c-ocores.yaml#

This should be rather named with vendor prefix, so:
opencores,i2c-ocores.yaml

> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: OpenCores I2C controller
> +
> +maintainers:
> +  - Peter Korsgaard <peter@korsgaard.com>
> +  - Andrew Lunn <andrew@lunn.ch>
> +
> +allOf:
> +  - $ref: /schemas/i2c/i2c-controller.yaml#
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
> +              - sifive,fu540-c000-i2c # Opencore based IP block FU540-C000 SoC
> +          - const: sifive,i2c0
> +      - const: opencores,i2c-ocores
> +      - const: aeroflexgaisler,i2cmst

The last two are just enum
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 0
> +
> +  clock-frequency:
> +    description: |
> +      Desired I2C bus clock frequency in Hz. As only Standard and Fast
> +      modes are supported, possible values are 100000 and 400000.

Add enum with the two values.

> +      Note:
> +      clock-frequency property is meant to control the bus frequency for i2c bus
> +      drivers, but it was incorrectly used to specify i2c controller input clock
> +      frequency. So the following rules are set to fix this situation:
> +      - if clock-frequency is present and neither opencores,ip-clock-frequency nor
> +        clocks are, then clock-frequency specifies i2c controller clock frequency.
> +        This is to keep backwards compatibility with setups using old DTB. i2c bus
> +        frequency is fixed at 100 KHz.
> +      - if clocks is present it specifies i2c controller clock. clock-frequency
> +        property specifies i2c bus frequency.
> +      - if opencores,ip-clock-frequency is present it specifies i2c controller
> +        clock frequency. clock-frequency property specifies i2c bus frequency.
> +    default: 100000
> +
> +  reg-io-width:
> +    $ref: /schemas/types.yaml#/definitions/uint32

No need for ref, it is coming from the dtschema.

> +    description: |
> +      io register width in bytes
> +    enum: [1, 2, 4]
> +
> +  reg-shift:
> +    $ref: /schemas/types.yaml#/definitions/uint32

No need for ref, it is coming from the dtschema.

> +    description: |
> +      device register offsets are shifted by this value

I guess 0 is default?

> +
> +  regstep:
> +    description: |
> +      deprecated, use reg-shift above
> +    deprecated: true
> +
> +  opencores,ip-clock-frequency:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: |
> +      Frequency of the controller clock in Hz. Mutually exclusive with clocks.
> +      See the note above.
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#address-cells"
> +  - "#size-cells"
> +
> +oneOf:
> +  - required:
> +      - opencores,ip-clock-frequency
> +  - required:
> +      - clocks

This is correct if your intention was to require one of these
properties, which seems to match the old bindings.

> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    i2c@a0000000 {
> +      #address-cells = <1>;
> +      #size-cells = <0>;
> +      compatible = "opencores,i2c-ocores";
> +      reg = <0xa0000000 0x8>;

Reorder the properties in the node so first goes compatible then reg,
then the rest.

> +      interrupts = <10>;
> +      opencores,ip-clock-frequency = <20000000>;
> +
> +      reg-shift = <0>;	/* 8 bit registers */
> +      reg-io-width = <1>;	/* 8 bit read/write */
> +
> +      dummy@60 {
> +        compatible = "dummy";
> +        reg = <0x60>;
> +      };
> +    };
> +
> +    i2c@b0000000 {
> +      #address-cells = <1>;
> +      #size-cells = <0>;
> +      compatible = "opencores,i2c-ocores";
> +      reg = <0xa0000000 0x8>;
> +      interrupts = <10>;
> +      clocks = <&osc>;
> +      clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
> +
> +      reg-shift = <0>;	/* 8 bit registers */
> +      reg-io-width = <1>;	/* 8 bit read/write */
> +
> +      dummy@60 {
> +        compatible = "dummy";
> +        reg = <0x60>;
> +      };
> +    };
> +...


Best regards,
Krzysztof