From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A5F5C4332F for ; Tue, 31 Oct 2023 08:51:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233576AbjJaIvZ (ORCPT ); Tue, 31 Oct 2023 04:51:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229656AbjJaIvX (ORCPT ); Tue, 31 Oct 2023 04:51:23 -0400 X-Greylist: delayed 399 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 31 Oct 2023 01:51:19 PDT Received: from mx4.sionneau.net (mx4.sionneau.net [51.15.250.1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8151191; Tue, 31 Oct 2023 01:51:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sionneau.net; s=selectormx4; t=1698741877; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Va8ZiGCtt0xAH03151MXq0eeco7iyUe1VrYD9JP5SDQ=; b=ua2XkeTT9tyr1+7uDBj8Ijq9xaSrAcF2YBKrgXZnCpIu10lr2BV5j1YvRv9QHbEcrOZMVi ONlccuoFj8zCGv7wCAWV+1dFx2qhPwtzWuPOFAg20FGhTEDYRXilNxeCBnbMvS61vaIJcI 7aER1yNzNfuyBShuQu3QqcfiNN5VWlE= Received: from [192.168.1.18] (91-171-21-26.subs.proxad.net [91.171.21.26]) by mx4.sionneau.net (OpenSMTPD) with ESMTPSA id a0fbea56 (TLSv1.3:TLS_AES_256_GCM_SHA384:256:NO); Tue, 31 Oct 2023 08:44:37 +0000 (UTC) Message-ID: <7ee0acbd-e332-4dc5-a6e6-0df58913ff71@sionneau.net> Date: Tue, 31 Oct 2023 09:44:36 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] i2c: designware: Fix corrupted memory seen in the ISR Content-Language: en-US To: Jan Bottorff , Wolfram Sang , Jarkko Nikula , Serge Semin , Yann Sionneau , Catalin Marinas , Will Deacon , Andy Shevchenko , Mika Westerberg , Jan Dabros , Andi Shyti , Philipp Zabel , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org References: <9219ad29-b9a3-4f07-81b5-43b4b6d9d178@os.amperecomputing.com> <3a305e74-2235-47ab-8564-0c594f24dc0a@os.amperecomputing.com> <1d56ceef-6573-43b9-a050-124c341a0698@linux.intel.com> Cc: Julian Vetter , Jonathan Borne From: Yann Sionneau In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Le 31/10/2023 à 01:12, Jan Bottorff a écrit : > On 10/26/2023 4:18 AM, Wolfram Sang wrote: >> So, someone wants to come up with a patch to move to non-relaxed io >> accessors? >> > Is the current thinking to just make writes to DW_IC_INTR_MASK use the > non-relaxed variant or something more broad? > > From a safest functioning viewpoint, we talked about making all > accessors default to non-relaxed variants. A couple of pretty good > arguments from knowledgeable people favored this. I know there also > was some concerns about potential performance impact this might have > although the counter argument was this is a pretty low speed device so > some extra cpu cycles on register accesses were not likely to degrade > overall performance. > > I could make the patch if we have consensus (or maintainers decision) > on which way to go: 1) only writes to DW_IC_INTR_MASK are non-relaxed, > 2) make all read/write accessors use the non-relaxed version. > > I'm personally in camp #2, safety first, performance fine tuning later > if needed. Latent missing barrier bugs are difficult and time > consuming to find. Fine with me, let's go for #2 :) Regards, -- Yann