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From: Jon Hunter <jonathanh@nvidia.com>
To: Akhil R <akhilrajeev@nvidia.com>,
	andi.shyti@kernel.org, digetx@gmail.com,
	linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-tegra@vger.kernel.org, thierry.reding@gmail.com,
	wsa+renesas@sang-engineering.com, wsa@kernel.org
Cc: kkartik@nvidia.com, ldewangan@nvidia.com, smangipudi@nvidia.com
Subject: Re: [PATCH v12 3/6] i2c: tegra: Update Tegra256 timing parameters
Date: Mon, 17 Nov 2025 09:52:34 +0000	[thread overview]
Message-ID: <811e364d-319a-4527-a4a7-627f3c926490@nvidia.com> (raw)
In-Reply-To: <20251115042632.69708-4-akhilrajeev@nvidia.com>



On 15/11/2025 04:26, Akhil R wrote:
> Update the timing parameters of Tegra256 so that the signals are complaint
> with the I2C specification for SCL low time.
> 
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> ---
>   drivers/i2c/busses/i2c-tegra.c | 16 +++++++---------
>   1 file changed, 7 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index c0382c9a0430..8a696c88882e 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -1677,14 +1677,13 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
>   	.setup_hold_time_hs_mode = 0x090909,
>   	.has_interface_timing_reg = true,
>   };
> -

Please don't remove this new line. Otherwise ...

>   static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
>   	.has_continue_xfer_support = true,
>   	.has_per_pkt_xfer_complete_irq = true,
>   	.clk_divisor_hs_mode = 7,
>   	.clk_divisor_std_mode = 0x7a,
>   	.clk_divisor_fast_mode = 0x40,
> -	.clk_divisor_fast_plus_mode = 0x19,
> +	.clk_divisor_fast_plus_mode = 0x14,
>   	.has_config_load_reg = true,
>   	.has_multi_master_mode = true,
>   	.has_slcg_override_reg = true,
> @@ -1695,14 +1694,13 @@ static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
>   	.has_apb_dma = false,
>   	.tlow_std_mode = 0x8,
>   	.thigh_std_mode = 0x7,
> -	.tlow_fast_mode = 0x3,
> -	.thigh_fast_mode = 0x3,
> -	.tlow_fastplus_mode = 0x3,
> -	.thigh_fastplus_mode = 0x3,
> +	.tlow_fast_mode = 0x4,
> +	.thigh_fast_mode = 0x2,
> +	.tlow_fastplus_mode = 0x4,
> +	.thigh_fastplus_mode = 0x4,
>   	.setup_hold_time_std_mode = 0x08080808,
> -	.setup_hold_time_fast_mode = 0x02020202,
> -	.setup_hold_time_fastplus_mode = 0x02020202,
> -	.setup_hold_time_hs_mode = 0x090909,
> +	.setup_hold_time_fast_mode = 0x04010101,
> +	.setup_hold_time_fastplus_mode = 0x04020202,
>   	.has_interface_timing_reg = true,
>   };
>   
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

Jon

-- 
nvpublic


  reply	other threads:[~2025-11-17  9:52 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-15  4:26 [PATCH v12 0/6] Updates for Tegra264 and Tegra256 Akhil R
2025-11-15  4:26 ` [PATCH v12 1/6] i2c: tegra: Do not configure DMA if not supported Akhil R
2025-11-15  4:26 ` [PATCH v12 2/6] i2c: tegra: Use separate variables for fast and fastplus Akhil R
2025-11-17  9:51   ` Jon Hunter
2025-11-15  4:26 ` [PATCH v12 3/6] i2c: tegra: Update Tegra256 timing parameters Akhil R
2025-11-17  9:52   ` Jon Hunter [this message]
2025-11-15  4:26 ` [PATCH v12 4/6] i2c: tegra: Add HS mode support Akhil R
2025-11-17 11:07   ` Jon Hunter
2025-11-18 11:09     ` Akhil R
2025-11-18 12:16       ` Jon Hunter
2025-11-18 12:25   ` Jon Hunter
2025-11-15  4:26 ` [PATCH v12 5/6] i2c: tegra: Add support for SW mutex register Akhil R
2025-11-15  4:26 ` [PATCH v12 6/6] i2c: tegra: Add Tegra264 support Akhil R

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