Re: [PATCH 1/1] i2c: designware: Fix wrong setting for {ss,fs}_{h,l}cnt registers

[Jarkko Nikula <jarkko.nikula@linux.intel.com>]

Hi

Sorry the delay.

On 7/17/24 9:59 AM, Adrian Huang wrote:
> From: Adrian Huang <ahuang12@lenovo.com>
> 
> When disabling CONFIG_X86_AMD_PLATFORM_DEVICE option, the driver
> 'drivers/acpi/acpi_apd.c' won't be compiled. This leads to a situation
> where BMC (Baseboard Management Controller) cannot retrieve the memory
> temperature via the i2c interface after i2c DW driver is loaded. Note
> that BMC can retrieve the memory temperature before booting into OS.
> 
> [Debugging Detail]
>    1. dev->pclk and dev->clk are NULL when calling devm_clk_get_optional()
>       in dw_i2c_plat_probe().
> 
>    2. The callings of i2c_dw_scl_hcnt() in i2c_dw_set_timings_master()
>       return 65528 (-8 in integer format) or 65533 (-3 in integer format).
>       The following log shows SS's HCNT/LCNT:
> 
>         i2c_designware AMDI0010:01: Standard Mode HCNT:LCNT = 65533:65535
> 
>    3. The callings of i2c_dw_scl_lcnt() in i2c_dw_set_timings_master()
>       return 65535 (-1 in integer format). The following log shows SS's
>       HCNT/LCNT:
> 
>         i2c_designware AMDI0010:01: Fast Mode HCNT:LCNT = 65533:65535
> 
>    4. i2c_dw_init_master() configures the register IC_SS_SCL_HCNT with
>       the value 65533. However, the DW i2c databook mentioned the value
>       cannot be higher than 65525. Quote from the DW i2c databook:
> 
>         NOTE: This register must not be programmed to a value higher than
>               65525, because DW_apb_i2c uses a 16-bit counter to flag an
>               I2C bus idle condition when this counter reaches a value of
>               IC_SS_SCL_HCNT + 10.
> 
>    5. Since ss_hcnt, ss_lcnt, fs_hcnt, and fs_lcnt are the invalid
>       values, we should not write the corresponding registers.
> 
> Fix the issue by returning 0 if ic_clk is 0 in i2c_dw_scl_{h,l}cnt().
> Then, do not write the corresponding registers if those values are 0.
> 
You are correct, indeed driver miscalculates those timing parameters in 
that case.

However debugging point of view below is misleading since it doesn't 
necessarily match with HW registers since they are not touched and have 
values what bootloader has left there.

	i2c_designware i2c_designware.0: Standard Mode HCNT:LCNT = 0:0

Would it work if patch just reads the dev->ss_hcnt, dev->ss_lcnt and so 
on from HW registers in case they and ic_clk are not set in 
i2c_dw_set_timings_master()? Then debug prints and HW values are in sync.