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Wed, 12 Feb 2025 15:03:29 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51CF3Tci031119 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Feb 2025 15:03:29 GMT Received: from [10.216.10.30] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 12 Feb 2025 07:03:24 -0800 Message-ID: <877d421f-18f8-461e-9b5e-e0e02ec3cbf0@quicinc.com> Date: Wed, 12 Feb 2025 20:33:20 +0530 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 RESEND 1/2] dmaengine: qcom: gpi: Add GPI Block event interrupt support To: Jyothi Kumar Seerapu , Vinod Koul , Andi Shyti , Sumit Semwal , =?UTF-8?Q?Christian_K=C3=B6nig?= CC: , , , , , , , References: <20250212120536.28879-1-quic_jseerapu@quicinc.com> <20250212120536.28879-2-quic_jseerapu@quicinc.com> Content-Language: en-US From: Mukesh Kumar Savaliya In-Reply-To: <20250212120536.28879-2-quic_jseerapu@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: lBhoDt0lBR6hg9D3iKhswVE2QiPlzVlx X-Proofpoint-ORIG-GUID: lBhoDt0lBR6hg9D3iKhswVE2QiPlzVlx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-12_04,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502120114 On 2/12/2025 5:35 PM, Jyothi Kumar Seerapu wrote: > GSI hardware generates an interrupt for each transfer completion. > For multiple messages within a single transfer, this results in > N interrupts for N messages, leading to significant software > interrupt latency. > > To mitigate this latency, utilize Block Event Interrupt (BEI) mechanism. > Enabling BEI instructs the GSI hardware to prevent interrupt generation > and BEI is disabled when an interrupt is necessary. > > When using BEI, consider splitting a single multi-message transfer into > chunks of 8 messages internally and so interrupts are not expected for > the first 7 message completions, only the last message triggers > an interrupt, indicating the completion of 8 messages. > > This BEI mechanism enhances overall transfer efficiency. > Acked-by: Mukesh Kumar Savaliya > Signed-off-by: Jyothi Kumar Seerapu > --- > > v4 -> v5: > - BEI flag naming changed from flags to bei_flag. > - QCOM_GPI_BLOCK_EVENT_IRQ macro is removed from qcom-gpi-dma.h > file, and Block event interrupt support is checked with bei_flag. > > v3 -> v4: > - API's added for Block event interrupt with multi descriptor support for > I2C is moved from qcom-gpi-dma.h file to I2C geni qcom driver file. > - gpi_multi_xfer_timeout_handler function is moved from GPI driver to > I2C driver. > > v2-> v3: > - Renamed gpi_multi_desc_process to gpi_multi_xfer_timeout_handler > - MIN_NUM_OF_MSGS_MULTI_DESC changed from 4 to 2 > - Added documentation for newly added changes in "qcom-gpi-dma.h" file > - Updated commit description. > > v1 -> v2: > - Changed dma_addr type from array of pointers to array. > - To support BEI functionality with the TRE size of 64 defined in GPI driver, > updated QCOM_GPI_MAX_NUM_MSGS to 16 and NUM_MSGS_PER_IRQ to 4. > > drivers/dma/qcom/gpi.c | 3 +++ > include/linux/dma/qcom-gpi-dma.h | 2 ++ > 2 files changed, 5 insertions(+) > > diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c > index 52a7c8f2498f..d925a8156317 100644 > --- a/drivers/dma/qcom/gpi.c > +++ b/drivers/dma/qcom/gpi.c > @@ -1693,6 +1693,9 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, > > tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE); > tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT); > + > + if (i2c->bei_flag) > + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_BEI); > } > > for (i = 0; i < tre_idx; i++) > diff --git a/include/linux/dma/qcom-gpi-dma.h b/include/linux/dma/qcom-gpi-dma.h > index 6680dd1a43c6..1060b7eac305 100644 > --- a/include/linux/dma/qcom-gpi-dma.h > +++ b/include/linux/dma/qcom-gpi-dma.h > @@ -65,6 +65,7 @@ enum i2c_op { > * @rx_len: receive length for buffer > * @op: i2c cmd > * @muli-msg: is part of multi i2c r-w msgs > + * @bei_flag: true for block event interrupt support > */ > struct gpi_i2c_config { > u8 set_config; > @@ -78,6 +79,7 @@ struct gpi_i2c_config { > u32 rx_len; > enum i2c_op op; > bool multi_msg; > + bool bei_flag; > }; > > #endif /* QCOM_GPI_DMA_H */