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low while ENABLE bit is disabled Thread-Topic: [PATCH v8] i2c: designware: fix master is holding SCL low while ENABLE bit is disabled Thread-Index: AQHbA0iDEXTpjDBp/E6xp/M7s9EaBrJQM8eAgACJC/D//5N/AIAAiqkw//+KBwCAAWKo0A== Date: Wed, 11 Sep 2024 01:37:43 +0000 Message-ID: <981861a36edc4b759e20f9be45d243c7@siengine.com> References: <9d181a45f3edf92364c9e6b729638f0b3f2e7baa.1725946886.git.kimriver.liu@siengine.com> <743187d2fde54a9ebf86d42e29eadfb4@siengine.com> <36e6d80999cf493f8a866fb013710682@siengine.com> In-Reply-To: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DKIM-Results: [10.8.1.61]; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:mail03.siengine.com 48B1bjPJ076135 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