From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B54714EC5B; Mon, 28 Apr 2025 16:14:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745856855; cv=none; b=RmyX4V7MuV03Wg0x8TzUdDUjmL14giuRKn4lANJHc7jMrqkxw86FIJwC+fF4ItPF/290fK1m56AhPlm1oGtUkJisOUqWqQP9zc0OLwWuEAa1WuvnV9ldb3htvQy9tDLJArEKfBDmOz5GENlkGckoHOMaN33cMIqdkZP09GKBVfI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745856855; c=relaxed/simple; bh=dieXJtGrsIb7S0Z/o5b2skI3aa8C+cWrhhwXmEj18w4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=hWIJ/x+O3suYHqyc4x3EzeJIa4GUP9lT6oOpoXoPU5/C1++7NZ6vzIYFNvThTZzH3Wd/ZAwq48fPgzmk2h/AQnHGmvh/WIuU4nTusKSrIpyRL1hoL6WcYfaCN2ThwB4fNBXqPGzb9XfBkl52QZ2T3JUFg+26d0k+PPiEPZnQDvc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aaZyEU+a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aaZyEU+a" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 38C3DC4CEE4; Mon, 28 Apr 2025 16:14:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745856854; bh=dieXJtGrsIb7S0Z/o5b2skI3aa8C+cWrhhwXmEj18w4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=aaZyEU+ave1e6P7101soHdSaiB3jtUwSkxF2MqNcRUCnSi5RvjV34OoRqVvrZQmZC EL9LSSPOCGHLT7U8lDmj5xaCrZiqkKZd8lg4wmomn+ndjJ4fD7qCW/1dbgZOfxWuD0 yJyyxYsGP56eeJGjepr/XCphxMq1cJy/IOYja5GWbgmc2LjeUamaUZfkPyzK//siBU 5WB2Folb7/dJtPFkqJfgXHkq4rdT2MjwkbudqINKQ/ownhjiCiVy35Y1acfZ0Sevzj 73m2vS6TOZXh+5zXCJLRJI07RBrXegkOqCIbmbXp8/kG+nVdi9RkJjK6FqWep5QqfX RhT2uwGofrOjw== Message-ID: <9d8abfc3-062e-4566-bf2f-42881ad36402@kernel.org> Date: Mon, 28 Apr 2025 11:14:09 -0500 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 0/5] AMD Zen debugging documentation To: Ingo Molnar , Jonathan Corbet Cc: Mario Limonciello , Yazen Ghannam , Thomas Gleixner , Ingo Molnar , Dave Hansen , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , Shyam Sundar S K , Hans de Goede , "open list:DOCUMENTATION" , open list , "open list:I2C/SMBUS CONTROLLER DRIVERS FOR PC" , "open list:AMD PMC DRIVER" , Borislav Petkov , Jean Delvare , Andi Shyti , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= References: <20250422234830.2840784-1-superm1@kernel.org> <87frhysyyp.fsf@trenco.lwn.net> Content-Language: en-US From: Mario Limonciello In-Reply-To: <87frhysyyp.fsf@trenco.lwn.net> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 4/23/2025 10:02 AM, Jonathan Corbet wrote: > Mario Limonciello writes: > >> From: Mario Limonciello >> >> Introduce documentation for debugging some issues on AMD zen hardware. >> As one of the debugging techniques read and add information for >> S5_RESET_STATUS register. > > I've been assuming that this work will go through the x86 tree; please > let me know if you'd like me to pick it up instead. > > Thanks, > > jon I think that's probably easier, patch 5 needs patch 1. Can you drop a tag for patch 1 and patch 5 (from doc perspective) so that Ingo can pull them through?