From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Kurtz Subject: Re: [PATCH] i2c: i801: Drop needless bit-wise OR Date: Fri, 3 Jun 2016 19:21:51 +0800 Message-ID: References: <20160525093702.64d7309c@endymion> <20160601113703.382c2a5f@endymion> <20160602134519.002f4776@endymion> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: Received: from mail-it0-f53.google.com ([209.85.214.53]:35876 "EHLO mail-it0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752133AbcFCLWN (ORCPT ); Fri, 3 Jun 2016 07:22:13 -0400 Received: by mail-it0-f53.google.com with SMTP id f67so6372538ith.1 for ; Fri, 03 Jun 2016 04:22:12 -0700 (PDT) In-Reply-To: <20160602134519.002f4776@endymion> Sender: linux-i2c-owner@vger.kernel.org List-Id: linux-i2c@vger.kernel.org To: Jean Delvare Cc: Linux I2C , Jarkko Nikula , Mika Westerberg , Wolfram Sang On Thu, Jun 2, 2016 at 7:45 PM, Jean Delvare wrote: > > On Wed, 1 Jun 2016 17:38:27 +0800, Daniel Kurtz wrote: > > On Wed, Jun 1, 2016 at 5:37 PM, Jean Delvare wrote: > > > > > > Hi Daniel, > > > > > > On Mon, 30 May 2016 22:07:55 +0800, Daniel Kurtz wrote: > > > > On Wed, May 25, 2016 at 3:37 PM, Jean Delvare wrote: > > > > > The interrupt handling code makes it look like several status values > > > > > may be merged together before being processed, while this will never > > > > > happen. Change from bit-wise OR to simple assignment to make it more > > > > > obvious and avoid misunderstanding. > > > > > > > > > > Signed-off-by: Jean Delvare > > > > > Cc: Daniel Kurtz > > > > > Cc: Jarkko Nikula > > > > > Cc: Mika Westerberg > > > > > Cc: Wolfram Sang > > > > > --- > > > > > Daniel, was there any reason for this bit-wise OR, which I may be > > > > > missing? > > > > > > > > The only thing I can think of is that I didn't want to assume that we > > > > would always clear priv->status before another interrupt arrived. > > > > > > Well my question is quite clear: can this actually happen? I can't see > > > how. > > > > I have no idea. You'd have to ask Intel, I guess. > > You wrote the code based on public documentation, I thought you would > know. But if you can't be bothered, never mind, I'll trust my > understanding of the code. Here is the documentation: http://www.intel.com/content/dam/doc/datasheet/io-controller-hub-6-datasheet.pdf Page 570 I thought maybe there were situations where you could get INTR and an error condition, but I don't see anything like that in the documentation, so I think you are right and only one bit will be set at a time. Reviewed-by: Daniel Kurtz > -- > Jean Delvare > SUSE L3 Support