Re: [PATCH v3 18/18] PCI: j721e: add suspend and resume support

Andy Shevchenko
2024-02-15T15:51:22Z

On Thu, Feb 15, 2024 at 04:18:03PM +0100, Thomas Richard wrote:
> From: Théo Lebrun <theo.lebrun@bootlin.com>
>
> Add suspend and resume support. Only the rc mode is supported.
>
> During the suspend stage PERST# is asserted, then deasserted during the
> resume stage.

...

> +#include <linux/clk-provider.h>
> #include <linux/clk.h>
> #include <linux/delay.h>
> #include <linux/gpio/consumer.h>
> @@ -18,10 +19,13 @@
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>

> +#include <linux/container_of.h>

Unordered.

...

> + ret = j721e_pcie_ctrl_init(pcie);
> + if (ret < 0) {
> + dev_err(dev, "j721e_pcie_ctrl_init failed\n");

Is there any guarantee this won't spam logs?

> + return ret;
> + }

...

> + /*
> + * This is not called explicitly in the probe, it is called by
> + * cdns_pcie_init_phy.

cdns_pcie_init_phy()

> + */
> + ret = cdns_pcie_enable_phy(pcie->cdns_pcie);
> + if (ret < 0) {
> + dev_err(dev, "cdns_pcie_enable_phy failed\n");
> + return -ENODEV;

A potential log spammer?

> + }

> + if (pcie->mode == PCI_MODE_RC) {
> + struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie);
> +
> + ret = clk_prepare_enable(pcie->refclk);
> + if (ret < 0) {
> + dev_err(dev, "clk_prepare_enable failed\n");

Ditto.

> + return -ENODEV;

Why is the error code shadowed?

> + }

...

> + if (pcie->reset_gpio) {
> + usleep_range(100, 200);

fsleep()

> + gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> + }

> + ret = cdns_pcie_host_link_setup(rc);
> + if (ret < 0) {
> + clk_disable_unprepare(pcie->refclk);
> + return ret;
> + }
> +
> + /*
> + * Reset internal status of BARs to force reinitialization in
> + * cdns_pcie_host_init().
> + */
> + for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
> + rc->avail_ib_bar[bar] = true;
> +
> + ret = cdns_pcie_host_init(rc);
> + if (ret)

No clock disabling?

> + return ret;
> + }

--
With Best Regards,
Andy Shevchenko