Re: [PATCH] i2c: ismt: Provide a DMA buffer for Interrupt Cause Logging

[Andy Shevchenko <andriy.shevchenko@linux.intel.com>]

On Wed, Apr 27, 2022 at 01:19:10PM +0300, Mika Westerberg wrote:
> Before sending a MSI the hardware writes information pertinent to the
> interrupt cause to a memory location pointed by SMTICL register. This
> memory holds three double words where the least significant bit tells
> whether the interrupt cause of master/target/error is valid. The driver
> does not use this but we need to set it up because otherwise it will
> perform DMA write to the default address (0) and this will cause an
> IOMMU fault such as below:
> 
>   DMAR: DRHD: handling fault status reg 2
>   DMAR: [DMA Write] Request device [00:12.0] PASID ffffffff fault addr 0
>         [fault reason 05] PTE Write access is not set
> 
> To prevent this from happening, provide a proper DMA buffer for this
> that then gets mapped by the IOMMU accordingly.

Reviewed-by: From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> ---
>  drivers/i2c/busses/i2c-ismt.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/i2c/busses/i2c-ismt.c b/drivers/i2c/busses/i2c-ismt.c
> index c0364314877e..c16157ee8c52 100644
> --- a/drivers/i2c/busses/i2c-ismt.c
> +++ b/drivers/i2c/busses/i2c-ismt.c
> @@ -82,6 +82,7 @@
>  
>  #define ISMT_DESC_ENTRIES	2	/* number of descriptor entries */
>  #define ISMT_MAX_RETRIES	3	/* number of SMBus retries to attempt */
> +#define ISMT_LOG_ENTRIES	3	/* number of interrupt cause log entries */
>  
>  /* Hardware Descriptor Constants - Control Field */
>  #define ISMT_DESC_CWRL	0x01	/* Command/Write Length */
> @@ -175,6 +176,8 @@ struct ismt_priv {
>  	u8 head;				/* ring buffer head pointer */
>  	struct completion cmp;			/* interrupt completion */
>  	u8 buffer[I2C_SMBUS_BLOCK_MAX + 16];	/* temp R/W data buffer */
> +	dma_addr_t log_dma;
> +	u32 *log;
>  };
>  
>  static const struct pci_device_id ismt_ids[] = {
> @@ -411,6 +414,9 @@ static int ismt_access(struct i2c_adapter *adap, u16 addr,
>  	memset(desc, 0, sizeof(struct ismt_desc));
>  	desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
>  
> +	/* Always clear the log entries */
> +	memset(priv->log, 0, ISMT_LOG_ENTRIES * sizeof(u32));
> +
>  	/* Initialize common control bits */
>  	if (likely(pci_dev_msi_enabled(priv->pci_dev)))
>  		desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
> @@ -708,6 +714,8 @@ static void ismt_hw_init(struct ismt_priv *priv)
>  	/* initialize the Master Descriptor Base Address (MDBA) */
>  	writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
>  
> +	writeq(priv->log_dma, priv->smba + ISMT_GR_SMTICL);
> +
>  	/* initialize the Master Control Register (MCTRL) */
>  	writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
>  
> @@ -795,6 +803,12 @@ static int ismt_dev_init(struct ismt_priv *priv)
>  	priv->head = 0;
>  	init_completion(&priv->cmp);
>  
> +	priv->log = dmam_alloc_coherent(&priv->pci_dev->dev,
> +					ISMT_LOG_ENTRIES * sizeof(u32),
> +					&priv->log_dma, GFP_KERNEL);
> +	if (!priv->log)
> +		return -ENOMEM;
> +
>  	return 0;
>  }
>  
> -- 
> 2.35.1
> 

-- 
With Best Regards,
Andy Shevchenko