[PATCH v3 0/2] i2c: Add new driver for Renesas RZ/V2M controller

[PATCH v3 0/2] i2c: Add new driver for Renesas RZ/V2M controller

[Phil Edworthy]

Hi,

The Renesas RZ/V2M SoC (r9a09g011) has a new i2c controller. This series
add the driver. One annoying problem is that the SoC uses a single reset
line for two i2c controllers, and unfortunately one of the controllers
is managed by some firmware, not by Linux. Therefore, the driver just
deasserts the reset.

v3:
  - dt-binding: Fix example indentation
  driver:
  - Lots of small fixes based on Andy Shevchenko's review
  - Use devm_reset_control_get_shared() instead of devm_reset_control_get() 

v2:
  dt-binding:
  - Use an enum and set the default for clock-frequency
  - Add resets property
  driver:
  - Use the new NOIRQ_SYSTEM_SLEEP_PM_OPS() as suggested by Arnd
  - Lots of small fixes based on Geert's review

Phil Edworthy (2):
  dt-bindings: i2c: Document RZ/V2M I2C controller
  i2c: Add Renesas RZ/V2M controller

 .../bindings/i2c/renesas,rzv2m.yaml           |  80 +++
 drivers/i2c/busses/Kconfig                    |  10 +
 drivers/i2c/busses/Makefile                   |   1 +
 drivers/i2c/busses/i2c-rzv2m.c                | 524 ++++++++++++++++++
 4 files changed, 615 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml
 create mode 100644 drivers/i2c/busses/i2c-rzv2m.c

-- 
2.34.1

[PATCH v3 1/2] dt-bindings: i2c: Document RZ/V2M I2C controller

[Phil Edworthy]

Document Renesas RZ/V2M (r9a09g011) I2C controller bindings.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v3:
 - Fix example indentation
v2:
 - Use an enum and set the default for clock-frequency
 - Add resets property
---
 .../bindings/i2c/renesas,rzv2m.yaml           | 80 +++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml

diff --git a/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml b/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml
new file mode 100644
index 000000000000..c46378efc123
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/renesas,rzv2m.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/V2M I2C Bus Interface
+
+maintainers:
+  - Phil Edworthy <phil.edworthy@renesas.com>
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,i2c-r9a09g011  # RZ/V2M
+      - const: renesas,rzv2m-i2c
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Data transmission/reception interrupt
+      - description: Status interrupt
+
+  interrupt-names:
+    items:
+      - const: tia
+      - const: tis
+
+  clock-frequency:
+    default: 100000
+    enum: [ 100000, 400000 ]
+    description:
+      Desired I2C bus clock frequency in Hz.
+
+  clocks:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - power-domains
+  - resets
+  - '#address-cells'
+  - '#size-cells'
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r9a09g011-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    i2c0: i2c@a4030000 {
+        compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c";
+        reg = <0xa4030000 0x80>;
+        interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
+        interrupt-names = "tia", "tis";
+        clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>;
+        resets = <&cpg R9A09G011_IIC_GPA_PRESETN>;
+        power-domains = <&cpg>;
+        clock-frequency = <100000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+    };
-- 
2.34.1

[PATCH v3 2/2] i2c: Add Renesas RZ/V2M controller

[Phil Edworthy]

Yet another i2c controller from Renesas that is found on the RZ/V2M
(r9a09g011) SoC. It can support only 100kHz and 400KHz operation.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v3:
 - Lots of small fixes based on Andy Shevchenko's review
 - Use devm_reset_control_get_shared() instead of devm_reset_control_get()
v2:
 - Use the new NOIRQ_SYSTEM_SLEEP_PM_OPS() as suggested by Arnd
 - Lots of small fixes based on Geert's review
---
 drivers/i2c/busses/Kconfig     |  10 +
 drivers/i2c/busses/Makefile    |   1 +
 drivers/i2c/busses/i2c-rzv2m.c | 524 +++++++++++++++++++++++++++++++++
 3 files changed, 535 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-rzv2m.c

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index b1d7069dd377..9e3f9eb1ea3c 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -984,6 +984,16 @@ config I2C_RK3X
 	  This driver can also be built as a module. If so, the module will
 	  be called i2c-rk3x.
 
+config I2C_RZV2M
+	tristate "Renesas RZ/V2M adapter"
+	depends on ARCH_RENESAS || COMPILE_TEST
+	help
+	  If you say yes to this option, support will be included for the
+	  Renesas RZ/V2M  I2C interface.
+
+	  This driver can also be built as a module.  If so, the module
+	  will be called i2c-rzv2m.
+
 config I2C_S3C2410
 	tristate "S3C/Exynos I2C Driver"
 	depends on ARCH_EXYNOS || ARCH_S3C24XX || ARCH_S3C64XX || \
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index b0a10e5d9ee9..7792ffc591f0 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_QCOM_GENI)	+= i2c-qcom-geni.o
 obj-$(CONFIG_I2C_QUP)		+= i2c-qup.o
 obj-$(CONFIG_I2C_RIIC)		+= i2c-riic.o
 obj-$(CONFIG_I2C_RK3X)		+= i2c-rk3x.o
+obj-$(CONFIG_I2C_RZV2M)		+= i2c-rzv2m.o
 obj-$(CONFIG_I2C_S3C2410)	+= i2c-s3c2410.o
 obj-$(CONFIG_I2C_SH7760)	+= i2c-sh7760.o
 obj-$(CONFIG_I2C_SH_MOBILE)	+= i2c-sh_mobile.o
diff --git a/drivers/i2c/busses/i2c-rzv2m.c b/drivers/i2c/busses/i2c-rzv2m.c
new file mode 100644
index 000000000000..197f71e8df33
--- /dev/null
+++ b/drivers/i2c/busses/i2c-rzv2m.c
@@ -0,0 +1,524 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for the Renesas RZ/V2M I2C unit
+ *
+ * Copyright (C) 2016-2022 Renesas Electronics Corporation
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/i2c.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+/* Register offsets */
+#define IICB0DAT	0x00		/* Data Register */
+#define IICB0CTL0	0x08		/* Control Register 0 */
+#define IICB0TRG	0x0C		/* Trigger Register */
+#define IICB0STR0	0x10		/* Status Register 0 */
+#define IICB0CTL1	0x20		/* Control Register 1 */
+#define IICB0WL		0x24		/* Low Level Width Setting Reg */
+#define IICB0WH		0x28		/* How Level Width Setting Reg */
+
+/* IICB0CTL0 */
+#define IICB0IICE	BIT(7)		/* I2C Enable */
+#define IICB0SLWT	BIT(1)		/* Interrupt Request Timing */
+#define IICB0SLAC	BIT(0)		/* Acknowledge */
+
+/* IICB0TRG */
+#define IICB0WRET	BIT(2)		/* Quit Wait Trigger */
+#define IICB0STT	BIT(1)		/* Create Start Condition Trigger */
+#define IICB0SPT	BIT(0)		/* Create Stop Condition Trigger */
+
+/* IICB0STR0 */
+#define IICB0SSAC	BIT(8)		/* Ack Flag */
+#define IICB0SSBS	BIT(6)		/* Bus Flag */
+#define IICB0SSSP	BIT(4)		/* Stop Condition Flag */
+
+/* IICB0CTL1 */
+#define IICB0MDSC	BIT(7)		/* Bus Mode */
+#define IICB0SLSE	BIT(1)		/* Start condition output */
+
+#define bit_setl(addr, val)		writel(readl(addr) | (val), (addr))
+#define bit_clrl(addr, val)		writel(readl(addr) & ~(val), (addr))
+
+struct rzv2m_i2c_priv {
+	void __iomem *base;
+	struct i2c_adapter adap;
+	struct clk *clk;
+	int bus_mode;
+	struct completion msg_tia_done;
+	u32 iicb0wl;
+	u32 iicb0wh;
+};
+
+enum bcr_index {
+	RZV2M_I2C_100K = 0,
+	RZV2M_I2C_400K,
+};
+
+struct bitrate_config {
+	unsigned int percent_low;
+	unsigned int min_hold_time_ns;
+};
+
+static const struct bitrate_config bitrate_configs[] = {
+	[RZV2M_I2C_100K] = { 47, 3450 },
+	[RZV2M_I2C_400K] = { 52, 900 },
+};
+
+static irqreturn_t rzv2m_i2c_tia_irq_handler(int this_irq, void *dev_id)
+{
+	struct rzv2m_i2c_priv *priv = dev_id;
+
+	complete(&priv->msg_tia_done);
+
+	return IRQ_HANDLED;
+}
+
+/* Calculate IICB0WL and IICB0WH */
+static int rzv2m_i2c_clock_calculate(struct device *dev,
+				     struct rzv2m_i2c_priv *priv)
+{
+	const struct bitrate_config *config;
+	unsigned int hold_time_ns;
+	unsigned int total_pclks;
+	unsigned int trf_pclks;
+	unsigned long pclk_hz;
+	struct i2c_timings t;
+	u32 trf_ns;
+
+	i2c_parse_fw_timings(dev, &t, true);
+
+	pclk_hz = clk_get_rate(priv->clk);
+	total_pclks = pclk_hz / t.bus_freq_hz;
+
+	trf_ns = t.scl_rise_ns + t.scl_fall_ns;
+	trf_pclks = mul_u64_u32_div(pclk_hz, trf_ns, NSEC_PER_SEC);
+
+	/* Config setting */
+	switch (t.bus_freq_hz) {
+	case I2C_MAX_FAST_MODE_FREQ:
+		priv->bus_mode = RZV2M_I2C_400K;
+		break;
+	case I2C_MAX_STANDARD_MODE_FREQ:
+		priv->bus_mode = RZV2M_I2C_100K;
+		break;
+	default:
+		dev_err(dev, "transfer speed is invalid\n");
+		return -EINVAL;
+	}
+	config = &bitrate_configs[priv->bus_mode];
+
+	/* IICB0WL = (percent_low / Transfer clock) x PCLK */
+	priv->iicb0wl = total_pclks * config->percent_low / 100;
+	if (priv->iicb0wl > (BIT(10) - 1))
+		return -EINVAL;
+
+	/* IICB0WH = ((percent_high / Transfer clock) x PCLK) - (tR + tF) */
+	priv->iicb0wh = total_pclks - priv->iicb0wl - trf_pclks;
+	if (priv->iicb0wh > (BIT(10) - 1))
+		return -EINVAL;
+
+	/*
+	 * Data hold time must be less than 0.9us in fast mode and
+	 * 3.45us in standard mode.
+	 * Data hold time = IICB0WL[9:2] / PCLK
+	 */
+	hold_time_ns = div64_ul((u64)(priv->iicb0wl >> 2) * NSEC_PER_SEC, pclk_hz);
+	if (hold_time_ns > config->min_hold_time_ns) {
+		dev_err(dev, "data hold time %dns is over %dns\n",
+			hold_time_ns, config->min_hold_time_ns);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void rzv2m_i2c_init(struct rzv2m_i2c_priv *priv)
+{
+	u32 i2c_ctl0;
+	u32 i2c_ctl1;
+
+	/* i2c disable */
+	writel(0, priv->base + IICB0CTL0);
+
+	/* IICB0CTL1 setting */
+	i2c_ctl1 = IICB0SLSE;
+	if (priv->bus_mode == RZV2M_I2C_400K)
+		i2c_ctl1 |= IICB0MDSC;
+	writel(i2c_ctl1, priv->base + IICB0CTL1);
+
+	/* IICB0WL IICB0WH setting */
+	writel(priv->iicb0wl, priv->base + IICB0WL);
+	writel(priv->iicb0wh, priv->base + IICB0WH);
+
+	/* i2c enable after setting */
+	i2c_ctl0 = IICB0SLWT | IICB0SLAC | IICB0IICE;
+	writel(i2c_ctl0, priv->base + IICB0CTL0);
+}
+
+static int rzv2m_i2c_write_with_ack(struct rzv2m_i2c_priv *priv, u32 data)
+{
+	unsigned long time_left;
+
+	reinit_completion(&priv->msg_tia_done);
+
+	writel(data, priv->base + IICB0DAT);
+
+	time_left = wait_for_completion_timeout(&priv->msg_tia_done,
+						priv->adap.timeout);
+	if (!time_left)
+		return -ETIMEDOUT;
+
+	/* Confirm ACK */
+	if ((readl(priv->base + IICB0STR0) & IICB0SSAC) != IICB0SSAC)
+		return -ENXIO;
+
+	return 0;
+}
+
+static int rzv2m_i2c_read_with_ack(struct rzv2m_i2c_priv *priv, u8 *data,
+				   bool last)
+{
+	unsigned long time_left;
+	u32 data_tmp;
+
+	reinit_completion(&priv->msg_tia_done);
+
+	/* Interrupt request timing : 8th clock */
+	bit_clrl(priv->base + IICB0CTL0, IICB0SLWT);
+
+	/* Exit the wait state */
+	writel(IICB0WRET, priv->base + IICB0TRG);
+
+	/* Wait for transaction */
+	time_left = wait_for_completion_timeout(&priv->msg_tia_done,
+						priv->adap.timeout);
+	if (!time_left)
+		return -ETIMEDOUT;
+
+	if (last) {
+		/* Disable ACK */
+		bit_clrl(priv->base + IICB0CTL0, IICB0SLAC);
+
+		/* Read data*/
+		data_tmp = readl(priv->base + IICB0DAT);
+
+		/* Interrupt request timing : 9th clock */
+		bit_setl(priv->base + IICB0CTL0, IICB0SLWT);
+
+		/* Exit the wait state */
+		writel(IICB0WRET, priv->base + IICB0TRG);
+
+		/* Wait for transaction */
+		time_left = wait_for_completion_timeout(&priv->msg_tia_done,
+							priv->adap.timeout);
+		if (!time_left)
+			return -ETIMEDOUT;
+
+		/* Enable ACK */
+		bit_setl(priv->base + IICB0CTL0, IICB0SLAC);
+	} else {
+		/* Read data */
+		data_tmp = readl(priv->base + IICB0DAT);
+	}
+
+	*data = data_tmp;
+
+	return 0;
+}
+
+static int rzv2m_i2c_send(struct rzv2m_i2c_priv *priv, struct i2c_msg *msg,
+			  unsigned int *count)
+{
+	unsigned int i;
+	int ret;
+
+	for (i = 0; i < msg->len; i++) {
+		ret = rzv2m_i2c_write_with_ack(priv, msg->buf[i]);
+		if (ret < 0)
+			return ret;
+	}
+	*count = i;
+
+	return 0;
+}
+
+static int rzv2m_i2c_receive(struct rzv2m_i2c_priv *priv, struct i2c_msg *msg,
+			     unsigned int *count)
+{
+	unsigned int i;
+	int ret;
+
+	for (i = 0; i < msg->len; i++) {
+		ret = rzv2m_i2c_read_with_ack(priv, &msg->buf[i],
+					      (msg->len - 1) == i);
+		if (ret < 0)
+			return ret;
+	}
+	*count = i;
+
+	return 0;
+}
+
+static int rzv2m_i2c_send_address(struct rzv2m_i2c_priv *priv,
+				  struct i2c_msg *msg)
+{
+	u32 addr;
+	int ret;
+
+	if (msg->flags & I2C_M_TEN) {
+		/* 10-bit address
+		 *   addr_1: 5'b11110 | addr[9:8] | (R/nW)
+		 *   addr_2: addr[7:0]
+		 */
+		addr = 0xf0 | ((msg->addr >> 7) & 0x06);
+		addr |= !!(msg->flags & I2C_M_RD);
+		/* Send 1st address(extend code) */
+		ret = rzv2m_i2c_write_with_ack(priv, addr);
+		if (ret)
+			return ret;
+
+		/* Send 2nd address */
+		ret = rzv2m_i2c_write_with_ack(priv, msg->addr & 0xff);
+	} else {
+		/* 7-bit address */
+		addr = i2c_8bit_addr_from_msg(msg);
+		ret = rzv2m_i2c_write_with_ack(priv, addr);
+	}
+
+	return ret;
+}
+
+static int rzv2m_i2c_stop_condition(struct rzv2m_i2c_priv *priv)
+{
+	u32 value;
+
+	/* Send stop condition */
+	writel(IICB0SPT, priv->base + IICB0TRG);
+	return readl_poll_timeout(priv->base + IICB0STR0,
+				  value, value & IICB0SSSP,
+				  100, jiffies_to_usecs(priv->adap.timeout));
+}
+
+static int rzv2m_i2c_master_xfer1(struct rzv2m_i2c_priv *priv,
+				  struct i2c_msg *msg, int stop)
+{
+	unsigned int count = 0;
+	int ret, read = !!(msg->flags & I2C_M_RD);
+
+	/* Send start condition */
+	writel(IICB0STT, priv->base + IICB0TRG);
+
+	ret = rzv2m_i2c_send_address(priv, msg);
+	if (!ret) {
+		if (read)
+			ret = rzv2m_i2c_receive(priv, msg, &count);
+		else
+			ret = rzv2m_i2c_send(priv, msg, &count);
+
+		if ((!ret) && stop)
+			ret = rzv2m_i2c_stop_condition(priv);
+	}
+
+	if (ret == -ENXIO)
+		rzv2m_i2c_stop_condition(priv);
+	else if (ret < 0)
+		rzv2m_i2c_init(priv);
+	else
+		ret = count;
+
+	return ret;
+}
+
+static int rzv2m_i2c_master_xfer(struct i2c_adapter *adap,
+				 struct i2c_msg *msgs, int num)
+{
+	struct rzv2m_i2c_priv *priv = i2c_get_adapdata(adap);
+	struct device *dev = priv->adap.dev.parent;
+	unsigned int i;
+	int ret;
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret < 0)
+		return ret;
+
+	if (readl(priv->base + IICB0STR0) & IICB0SSBS) {
+		ret = -EAGAIN;
+		goto out;
+	}
+
+	/* I2C main transfer */
+	for (i = 0; i < num; i++) {
+		ret = rzv2m_i2c_master_xfer1(priv, &msgs[i], (i == (num - 1)));
+		if (ret < 0)
+			goto out;
+	}
+	ret = num;
+
+out:
+	pm_runtime_mark_last_busy(dev);
+	pm_runtime_put_autosuspend(dev);
+
+	return ret;
+}
+
+static u32 rzv2m_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
+	       I2C_FUNC_10BIT_ADDR;
+}
+
+static const struct i2c_adapter_quirks rzv2m_i2c_quirks = {
+	.flags = I2C_AQ_NO_ZERO_LEN,
+};
+
+static struct i2c_algorithm rzv2m_i2c_algo = {
+	.master_xfer = rzv2m_i2c_master_xfer,
+	.functionality = rzv2m_i2c_func,
+};
+
+static const struct of_device_id rzv2m_i2c_ids[] = {
+	{ .compatible = "renesas,rzv2m-i2c" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, rzv2m_i2c_ids);
+
+static int rzv2m_i2c_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct rzv2m_i2c_priv *priv;
+	struct reset_control *rstc;
+	struct i2c_adapter *adap;
+	struct resource *res;
+	int irq, ret;
+
+	priv = devm_kzalloc(dev, sizeof(struct rzv2m_i2c_priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk))
+		return dev_err_probe(dev, PTR_ERR(priv->clk), "Can't get clock\n");
+
+	rstc = devm_reset_control_get_shared(dev, NULL);
+	if (IS_ERR(rstc))
+		return dev_err_probe(dev, PTR_ERR(rstc), "Missing reset ctrl\n");
+	/*
+	 * The reset also affects other HW that is not under the control
+	 * of Linux. Therefore, all we can do is deassert the reset.
+	 */
+	reset_control_deassert(rstc);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
+
+	ret = devm_request_irq(dev, irq, rzv2m_i2c_tia_irq_handler, 0,
+			       dev_name(dev), priv);
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "Unable to request irq %d\n", irq);
+
+	adap = &priv->adap;
+	adap->nr = pdev->id;
+	adap->algo = &rzv2m_i2c_algo;
+	adap->quirks = &rzv2m_i2c_quirks;
+	adap->class = I2C_CLASS_DEPRECATED;
+	adap->dev.parent = dev;
+	adap->owner = THIS_MODULE;
+	device_set_node(&adap->dev, dev_fwnode(dev));
+	i2c_set_adapdata(adap, priv);
+	strscpy(adap->name, pdev->name, sizeof(adap->name));
+	init_completion(&priv->msg_tia_done);
+
+	ret = rzv2m_i2c_clock_calculate(dev, priv);
+	if (ret < 0)
+		return ret;
+
+	pm_runtime_enable(dev);
+
+	pm_runtime_get_sync(dev);
+	rzv2m_i2c_init(priv);
+	pm_runtime_put(dev);
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = i2c_add_numbered_adapter(adap);
+	if (ret < 0)
+		pm_runtime_disable(dev);
+
+	return ret;
+}
+
+static int rzv2m_i2c_remove(struct platform_device *pdev)
+{
+	struct rzv2m_i2c_priv *priv = platform_get_drvdata(pdev);
+	struct device *dev = priv->adap.dev.parent;
+
+	i2c_del_adapter(&priv->adap);
+	bit_clrl(priv->base + IICB0CTL0, IICB0IICE);
+	pm_runtime_disable(dev);
+
+	return 0;
+}
+
+static int rzv2m_i2c_suspend(struct device *dev)
+{
+	struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
+
+	pm_runtime_get_sync(dev);
+	bit_clrl(priv->base + IICB0CTL0, IICB0IICE);
+	pm_runtime_put(dev);
+
+	return 0;
+}
+
+static int rzv2m_i2c_resume(struct device *dev)
+{
+	struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
+	int ret;
+
+	ret = rzv2m_i2c_clock_calculate(dev, priv);
+	if (ret < 0)
+		return ret;
+
+	pm_runtime_get_sync(dev);
+	rzv2m_i2c_init(priv);
+	pm_runtime_put(dev);
+
+	return 0;
+}
+
+static const struct dev_pm_ops rzv2m_i2c_pm_ops = {
+	NOIRQ_SYSTEM_SLEEP_PM_OPS(rzv2m_i2c_suspend, rzv2m_i2c_resume)
+};
+
+static struct platform_driver rzv2m_i2c_driver = {
+	.driver = {
+		.name = "rzv2m-i2c",
+		.of_match_table = rzv2m_i2c_ids,
+		.pm = pm_sleep_ptr(&rzv2m_i2c_pm_ops),
+	},
+	.probe	= rzv2m_i2c_probe,
+	.remove	= rzv2m_i2c_remove,
+};
+module_platform_driver(rzv2m_i2c_driver);
+
+MODULE_DESCRIPTION("RZ/V2M I2C bus driver");
+MODULE_AUTHOR("Renesas Electronics Corporation");
+MODULE_LICENSE("GPL");
-- 
2.34.1

Re: [PATCH v3 2/2] i2c: Add Renesas RZ/V2M controller

[Andy Shevchenko]

On Fri, Jul 01, 2022 at 05:39:16PM +0100, Phil Edworthy wrote:
> Yet another i2c controller from Renesas that is found on the RZ/V2M
> (r9a09g011) SoC. It can support only 100kHz and 400KHz operation.

...

> +		/* 10-bit address
> +		 *   addr_1: 5'b11110 | addr[9:8] | (R/nW)
> +		 *   addr_2: addr[7:0]
> +		 */

/*
 * Multi-line comments should be
 * formatted like in this example.
 * (Of course use as much space up
 * to 80 as possible.)
 */

Ditto for other done in similar way, if any.

...

> +		addr = 0xf0 | ((msg->addr >> 7) & 0x06);

GENMASK() ?

...

> +	if (!ret) {
> +		if (read)
> +			ret = rzv2m_i2c_receive(priv, msg, &count);
> +		else
> +			ret = rzv2m_i2c_send(priv, msg, &count);

> +		if ((!ret) && stop)

Too many parentheses.

> +			ret = rzv2m_i2c_stop_condition(priv);
> +	}

...

> +		ret = rzv2m_i2c_master_xfer1(priv, &msgs[i], (i == (num - 1)));

Too many parentheses.

> +		if (ret < 0)
> +			goto out;

...

> +static const struct of_device_id rzv2m_i2c_ids[] = {
> +	{ .compatible = "renesas,rzv2m-i2c" },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, rzv2m_i2c_ids);

This can be moved after the ->probe() closer to the actual user of the table.

...

> +	priv = devm_kzalloc(dev, sizeof(struct rzv2m_i2c_priv), GFP_KERNEL);

sizeof(*priv)

> +	if (!priv)
> +		return -ENOMEM;

...

> +static int rzv2m_i2c_suspend(struct device *dev)
> +{
> +	struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);

> +	pm_runtime_get_sync(dev);

Isn't guaranteed by the runtime PM that device is runtime powered on the system
suspend?

> +	bit_clrl(priv->base + IICB0CTL0, IICB0IICE);
> +	pm_runtime_put(dev);
> +
> +	return 0;
> +}

...

> +static int rzv2m_i2c_resume(struct device *dev)
> +{
> +	struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
> +	int ret;
> +
> +	ret = rzv2m_i2c_clock_calculate(dev, priv);
> +	if (ret < 0)
> +		return ret;
> +
> +	pm_runtime_get_sync(dev);

I'm not sure how it's suppose to work. Isn't it a no-op here?

> +	rzv2m_i2c_init(priv);
> +	pm_runtime_put(dev);
> +
> +	return 0;
> +}

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v3 2/2] i2c: Add Renesas RZ/V2M controller

[Geert Uytterhoeven]

Hi Andy,

On Sat, Jul 2, 2022 at 1:51 PM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
> On Fri, Jul 01, 2022 at 05:39:16PM +0100, Phil Edworthy wrote:
> > Yet another i2c controller from Renesas that is found on the RZ/V2M
> > (r9a09g011) SoC. It can support only 100kHz and 400KHz operation.

>
> > +static int rzv2m_i2c_suspend(struct device *dev)
> > +{
> > +     struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
>
> > +     pm_runtime_get_sync(dev);

pm_runtime_resume_and_get() ;-)

>
> Isn't guaranteed by the runtime PM that device is runtime powered on the system
> suspend?

No, as this is a system sleep callback.

>
> > +     bit_clrl(priv->base + IICB0CTL0, IICB0IICE);
> > +     pm_runtime_put(dev);
> > +
> > +     return 0;
> > +}
>
> ...
>
> > +static int rzv2m_i2c_resume(struct device *dev)
> > +{
> > +     struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
> > +     int ret;
> > +
> > +     ret = rzv2m_i2c_clock_calculate(dev, priv);
> > +     if (ret < 0)
> > +             return ret;
> > +
> > +     pm_runtime_get_sync(dev);

pm_runtime_resume_and_get() ;-)

>
> I'm not sure how it's suppose to work. Isn't it a no-op here?

No, as this is a system sleep callback.

>
> > +     rzv2m_i2c_init(priv);
> > +     pm_runtime_put(dev);
> > +
> > +     return 0;
> > +}

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 2/2] i2c: Add Renesas RZ/V2M controller

[Andy Shevchenko]

On Sun, Jul 03, 2022 at 10:41:45AM +0200, Geert Uytterhoeven wrote:
> On Sat, Jul 2, 2022 at 1:51 PM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
> > On Fri, Jul 01, 2022 at 05:39:16PM +0100, Phil Edworthy wrote:
> > > Yet another i2c controller from Renesas that is found on the RZ/V2M
> > > (r9a09g011) SoC. It can support only 100kHz and 400KHz operation.

...

> > > +     pm_runtime_get_sync(dev);
> 
> pm_runtime_resume_and_get() ;-)

This makes sense only if we test for error. Otherwise the put might imbalance
counter.

...

> > Isn't guaranteed by the runtime PM that device is runtime powered on the system
> > suspend?
> 
> No, as this is a system sleep callback.

Hmm... Indeed. Code also suggested what you told. Thanks!

-- 
With Best Regards,
Andy Shevchenko

RE: [PATCH v3 2/2] i2c: Add Renesas RZ/V2M controller

[Phil Edworthy]

Hi Andy,

On 03 July 2022 16:17 Andy Shevchenko wrote:
> On Sun, Jul 03, 2022 at 10:41:45AM +0200, Geert Uytterhoeven wrote:
> > On Sat, Jul 2, 2022 at 1:51 PM Andy Shevchenko
> > <andriy.shevchenko@linux.intel.com> wrote:
> > > On Fri, Jul 01, 2022 at 05:39:16PM +0100, Phil Edworthy wrote:
> > > > Yet another i2c controller from Renesas that is found on the RZ/V2M
> > > > (r9a09g011) SoC. It can support only 100kHz and 400KHz operation.
> 
> ...
All other suggested changes are ok.


> > > > +     pm_runtime_get_sync(dev);
> >
> > pm_runtime_resume_and_get() ;-)
> 
> This makes sense only if we test for error. Otherwise the put might
> imbalance
> counter.
I added code to check the return value and to my surprise it returned
-EACCES.
Some digging later, this only happens when I have an i2c controller
enabled that doesn't have any children.

rpm_resume() returns -EACCES [1] because runtime_status and last_status
are set to RPM_SUSPENDED.

The i2c controller that does have a child has runtime_status = RPM_ACTIVE
as there is a call to pm_runtime_resume_and_get() on it due to the i2c
controller performing an i2c transfer for the slave device.

I am currently struggling to work out why this is happening...

Thanks
Phil

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/base/power/runtime.c?h=v5.19-rc5#n773

RE: [PATCH v3 2/2] i2c: Add Renesas RZ/V2M controller

[Phil Edworthy]

Hi Andy,

On 07 July 2022 08:21 Phil Edworthy wrote:
> On 03 July 2022 16:17 Andy Shevchenko wrote:
> > On Sun, Jul 03, 2022 at 10:41:45AM +0200, Geert Uytterhoeven wrote:
> > > On Sat, Jul 2, 2022 at 1:51 PM Andy Shevchenko
> > > <andriy.shevchenko@linux.intel.com> wrote:
> > > > On Fri, Jul 01, 2022 at 05:39:16PM +0100, Phil Edworthy wrote:
> > > > > Yet another i2c controller from Renesas that is found on the
> RZ/V2M
> > > > > (r9a09g011) SoC. It can support only 100kHz and 400KHz operation.
> >
> > ...
> All other suggested changes are ok.
> 
> 
> > > > > +     pm_runtime_get_sync(dev);
> > >
> > > pm_runtime_resume_and_get() ;-)
> >
> > This makes sense only if we test for error. Otherwise the put might
> > imbalance
> > counter.
> I added code to check the return value and to my surprise it returned
> -EACCES.
> Some digging later, this only happens when I have an i2c controller
> enabled that doesn't have any children.
> 
> rpm_resume() returns -EACCES [1] because runtime_status and last_status
> are set to RPM_SUSPENDED.
> 
> The i2c controller that does have a child has runtime_status = RPM_ACTIVE
> as there is a call to pm_runtime_resume_and_get() on it due to the i2c
> controller performing an i2c transfer for the slave device.
> 
> I am currently struggling to work out why this is happening...

First pm_suspend() works it's way down to __pm_runtime_disable():
  __pm_runtime_disable+0x134/0x1e0
  __device_suspend_late+0x28/0x1c4
  dpm_suspend_late+0x158/0x230
  suspend_devices_and_enter+0x1c8/0x4b4
  pm_suspend+0x210/0x28c
At the end of which, runtime_status and last_status are both RPM_SUSPENDED,
and disable_depth = 1 [1]

After that rzv2m_i2c_suspend() is called triggering the EACCES error
condition [2]:
  rpm_resume+0x338/0x630
  __pm_runtime_resume+0x4c/0x80
  rzv2m_i2c_suspend+0x24/0xb0
  pm_generic_suspend_noirq+0x30/0x50
  genpd_finish_suspend+0xb0/0x130
  genpd_suspend_noirq+0x14/0x20
  __device_suspend_noirq+0x68/0x1d0
  dpm_noirq_suspend_devices+0x110/0x1dc
  dpm_suspend_noirq+0x24/0xa0
  suspend_devices_and_enter+0x2f0/0x4b4
  pm_suspend+0x210/0x28c

I think using runtime PM from within driver suspend/resume is simply not
supported. However I had some difficulty following the runtime PM code,
so I could be wrong.

Phil

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/base/power/runtime.c?h=v5.19-rc5#n1466
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/base/power/runtime.c?h=v5.19-rc5#n773

Re: [PATCH v3 2/2] i2c: Add Renesas RZ/V2M controller

[Geert Uytterhoeven]

Hi Phil,

On Thu, Jul 7, 2022 at 6:37 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> On 07 July 2022 08:21 Phil Edworthy wrote:
> > On 03 July 2022 16:17 Andy Shevchenko wrote:
> > > On Sun, Jul 03, 2022 at 10:41:45AM +0200, Geert Uytterhoeven wrote:
> > > > On Sat, Jul 2, 2022 at 1:51 PM Andy Shevchenko
> > > > <andriy.shevchenko@linux.intel.com> wrote:
> > > > > On Fri, Jul 01, 2022 at 05:39:16PM +0100, Phil Edworthy wrote:
> > > > > > Yet another i2c controller from Renesas that is found on the
> > RZ/V2M
> > > > > > (r9a09g011) SoC. It can support only 100kHz and 400KHz operation.
> > >
> > > ...
> > All other suggested changes are ok.
> >
> >
> > > > > > +     pm_runtime_get_sync(dev);
> > > >
> > > > pm_runtime_resume_and_get() ;-)
> > >
> > > This makes sense only if we test for error. Otherwise the put might
> > > imbalance
> > > counter.
> > I added code to check the return value and to my surprise it returned
> > -EACCES.
> > Some digging later, this only happens when I have an i2c controller
> > enabled that doesn't have any children.
> >
> > rpm_resume() returns -EACCES [1] because runtime_status and last_status
> > are set to RPM_SUSPENDED.
> >
> > The i2c controller that does have a child has runtime_status = RPM_ACTIVE
> > as there is a call to pm_runtime_resume_and_get() on it due to the i2c
> > controller performing an i2c transfer for the slave device.
> >
> > I am currently struggling to work out why this is happening...
>
> First pm_suspend() works it's way down to __pm_runtime_disable():
>   __pm_runtime_disable+0x134/0x1e0
>   __device_suspend_late+0x28/0x1c4
>   dpm_suspend_late+0x158/0x230
>   suspend_devices_and_enter+0x1c8/0x4b4
>   pm_suspend+0x210/0x28c
> At the end of which, runtime_status and last_status are both RPM_SUSPENDED,
> and disable_depth = 1 [1]
>
> After that rzv2m_i2c_suspend() is called triggering the EACCES error
> condition [2]:
>   rpm_resume+0x338/0x630
>   __pm_runtime_resume+0x4c/0x80
>   rzv2m_i2c_suspend+0x24/0xb0
>   pm_generic_suspend_noirq+0x30/0x50
>   genpd_finish_suspend+0xb0/0x130
>   genpd_suspend_noirq+0x14/0x20
>   __device_suspend_noirq+0x68/0x1d0
>   dpm_noirq_suspend_devices+0x110/0x1dc
>   dpm_suspend_noirq+0x24/0xa0
>   suspend_devices_and_enter+0x2f0/0x4b4
>   pm_suspend+0x210/0x28c
>
> I think using runtime PM from within driver suspend/resume is simply not
> supported. However I had some difficulty following the runtime PM code,
> so I could be wrong.

Oh, it's a NOIRQ system sleep op. You indeed cannot use runtime resume
from such a callback, as the latter may sleep.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v3 2/2] i2c: Add Renesas RZ/V2M controller

[Phil Edworthy]

Hi Geert,

On 07 July 2022 18:46 Geert Uytterhoeven wrote:
> On Thu, Jul 7, 2022 at 6:37 PM Phil Edworthy wrote:
> > On 07 July 2022 08:21 Phil Edworthy wrote:
> > > On 03 July 2022 16:17 Andy Shevchenko wrote:
> > > > On Sun, Jul 03, 2022 at 10:41:45AM +0200, Geert Uytterhoeven wrote:
> > > > > On Sat, Jul 2, 2022 at 1:51 PM Andy Shevchenko
> > > > > <andriy.shevchenko@linux.intel.com> wrote:
> > > > > > On Fri, Jul 01, 2022 at 05:39:16PM +0100, Phil Edworthy wrote:
> > > > > > > Yet another i2c controller from Renesas that is found on the
> > > RZ/V2M
> > > > > > > (r9a09g011) SoC. It can support only 100kHz and 400KHz
> operation.
> > > >
> > > > ...
> > > All other suggested changes are ok.
> > >
> > >
> > > > > > > +     pm_runtime_get_sync(dev);
> > > > >
> > > > > pm_runtime_resume_and_get() ;-)
> > > >
> > > > This makes sense only if we test for error. Otherwise the put might
> > > > imbalance
> > > > counter.
> > > I added code to check the return value and to my surprise it returned
> > > -EACCES.
> > > Some digging later, this only happens when I have an i2c controller
> > > enabled that doesn't have any children.
> > >
> > > rpm_resume() returns -EACCES [1] because runtime_status and
> last_status
> > > are set to RPM_SUSPENDED.
> > >
> > > The i2c controller that does have a child has runtime_status =
> RPM_ACTIVE
> > > as there is a call to pm_runtime_resume_and_get() on it due to the i2c
> > > controller performing an i2c transfer for the slave device.
> > >
> > > I am currently struggling to work out why this is happening...
> >
> > First pm_suspend() works it's way down to __pm_runtime_disable():
> >   __pm_runtime_disable+0x134/0x1e0
> >   __device_suspend_late+0x28/0x1c4
> >   dpm_suspend_late+0x158/0x230
> >   suspend_devices_and_enter+0x1c8/0x4b4
> >   pm_suspend+0x210/0x28c
> > At the end of which, runtime_status and last_status are both
> RPM_SUSPENDED,
> > and disable_depth = 1 [1]
> >
> > After that rzv2m_i2c_suspend() is called triggering the EACCES error
> > condition [2]:
> >   rpm_resume+0x338/0x630
> >   __pm_runtime_resume+0x4c/0x80
> >   rzv2m_i2c_suspend+0x24/0xb0
> >   pm_generic_suspend_noirq+0x30/0x50
> >   genpd_finish_suspend+0xb0/0x130
> >   genpd_suspend_noirq+0x14/0x20
> >   __device_suspend_noirq+0x68/0x1d0
> >   dpm_noirq_suspend_devices+0x110/0x1dc
> >   dpm_suspend_noirq+0x24/0xa0
> >   suspend_devices_and_enter+0x2f0/0x4b4
> >   pm_suspend+0x210/0x28c
> >
> > I think using runtime PM from within driver suspend/resume is simply not
> > supported. However I had some difficulty following the runtime PM code,
> > so I could be wrong.
> 
> Oh, it's a NOIRQ system sleep op. You indeed cannot use runtime resume
> from such a callback, as the latter may sleep.
Thanks for confirming this.

I believe i2c controller driver should use NOIRQ system sleep ops as i2c
children may need to send I2C messages during suspend, and the noirq
sleep ops are called after the late sleep ops (used by some i2c children
drivers).

So should I just use clk_prepare_enable() and clk_prepare_enable()
within the i2c controller's suspend and resume?

BR
Phil

Re: [PATCH v3 2/2] i2c: Add Renesas RZ/V2M controller

[Geert Uytterhoeven]

Hi Phil,

On Thu, Jul 7, 2022 at 8:47 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> On 07 July 2022 18:46 Geert Uytterhoeven wrote:
> > On Thu, Jul 7, 2022 at 6:37 PM Phil Edworthy wrote:
> > > On 07 July 2022 08:21 Phil Edworthy wrote:
> > > > On 03 July 2022 16:17 Andy Shevchenko wrote:
> > > > > On Sun, Jul 03, 2022 at 10:41:45AM +0200, Geert Uytterhoeven wrote:
> > > > > > On Sat, Jul 2, 2022 at 1:51 PM Andy Shevchenko
> > > > > > <andriy.shevchenko@linux.intel.com> wrote:
> > > > > > > On Fri, Jul 01, 2022 at 05:39:16PM +0100, Phil Edworthy wrote:
> > > > > > > > Yet another i2c controller from Renesas that is found on the
> > > > RZ/V2M
> > > > > > > > (r9a09g011) SoC. It can support only 100kHz and 400KHz
> > operation.
> > > > >
> > > > > ...
> > > > All other suggested changes are ok.
> > > >
> > > >
> > > > > > > > +     pm_runtime_get_sync(dev);
> > > > > >
> > > > > > pm_runtime_resume_and_get() ;-)
> > > > >
> > > > > This makes sense only if we test for error. Otherwise the put might
> > > > > imbalance
> > > > > counter.
> > > > I added code to check the return value and to my surprise it returned
> > > > -EACCES.
> > > > Some digging later, this only happens when I have an i2c controller
> > > > enabled that doesn't have any children.
> > > >
> > > > rpm_resume() returns -EACCES [1] because runtime_status and
> > last_status
> > > > are set to RPM_SUSPENDED.
> > > >
> > > > The i2c controller that does have a child has runtime_status =
> > RPM_ACTIVE
> > > > as there is a call to pm_runtime_resume_and_get() on it due to the i2c
> > > > controller performing an i2c transfer for the slave device.
> > > >
> > > > I am currently struggling to work out why this is happening...
> > >
> > > First pm_suspend() works it's way down to __pm_runtime_disable():
> > >   __pm_runtime_disable+0x134/0x1e0
> > >   __device_suspend_late+0x28/0x1c4
> > >   dpm_suspend_late+0x158/0x230
> > >   suspend_devices_and_enter+0x1c8/0x4b4
> > >   pm_suspend+0x210/0x28c
> > > At the end of which, runtime_status and last_status are both
> > RPM_SUSPENDED,
> > > and disable_depth = 1 [1]
> > >
> > > After that rzv2m_i2c_suspend() is called triggering the EACCES error
> > > condition [2]:
> > >   rpm_resume+0x338/0x630
> > >   __pm_runtime_resume+0x4c/0x80
> > >   rzv2m_i2c_suspend+0x24/0xb0
> > >   pm_generic_suspend_noirq+0x30/0x50
> > >   genpd_finish_suspend+0xb0/0x130
> > >   genpd_suspend_noirq+0x14/0x20
> > >   __device_suspend_noirq+0x68/0x1d0
> > >   dpm_noirq_suspend_devices+0x110/0x1dc
> > >   dpm_suspend_noirq+0x24/0xa0
> > >   suspend_devices_and_enter+0x2f0/0x4b4
> > >   pm_suspend+0x210/0x28c
> > >
> > > I think using runtime PM from within driver suspend/resume is simply not
> > > supported. However I had some difficulty following the runtime PM code,
> > > so I could be wrong.
> >
> > Oh, it's a NOIRQ system sleep op. You indeed cannot use runtime resume
> > from such a callback, as the latter may sleep.
> Thanks for confirming this.
>
> I believe i2c controller driver should use NOIRQ system sleep ops as i2c
> children may need to send I2C messages during suspend, and the noirq
> sleep ops are called after the late sleep ops (used by some i2c children
> drivers).
>
> So should I just use clk_prepare_enable() and clk_prepare_enable()
> within the i2c controller's suspend and resume?

That's one option.
There's also i2c_mark_adapter_suspended().

And if you care about sending messages in atomic/noirq context,
you want to implement i2c_algorithm.master_xfer_atomic().

You may want to have a look at drivers/i2c/busses/i2c-sh_mobile.c,
which is used to control the PMIC on R-Car SoCs.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds